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參數(shù)資料
| 型號： | ADV7330 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit Triple DAC Video Encoder |
| 中文描述： | 多格式11位DAC的視頻編碼器三 |
| 文件頁數(shù)： | 32/76頁 |
| 文件大?。?/td> | 1378K |
| 代理商： | ADV7330 |
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REV. B
–32–
ADV7330
LCC1
GLL
P17–P10
COMPOSITE VIDEO
e.g., VCR OR CABLE
CLKIN
RTC_SCR_TR
DAC A
DAC B
DAC C
Y7–Y0
RTC
LOW
COUNT START
128
TIME SLOT: 01
13
0
14 BITS
SUBCARRIER
PHASE
14
21
19
F
SC
PLL INCREMENT
1
VALID
SAMPLE
INVALID
SAMPLE
8/LINE
LOCKED
CLOCK
6768
4 BITS
RESERVED
0
SEQUENCE
BIT
2
RESET
BIT
3
RESERVED
5 BITS
RESERVED
ADV7330
VIDEO
DECODER
ADV7183A
NOTES
1
F
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7330, F
DSS REGISTER IS F
PLL INCREMENTS BITS 21:0 PLUS
BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY
REGISTERS OF THE ADV7330.
2
SEQUENCE BIT.
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED.
NTSC: 0 = NO CHANGE.
3
RESET BIT. RESET ADV7330 DSS.
Figure 23. RTC Timing and Connections
XXXXXX
XXXXXX
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
RESET
DIGITAL TIMING
DACs
A, B, C
PIXEL DATA
VALID
Figure 24.
RESET
Timing Sequence
Reset Sequence
A reset is activated with a high-to-low transition on the
RESET
pin
(Pin 33) according to the Timing Specifications. The ADV7330
will revert to the default output configuration.
Figure 24 illustrates the
RESET
sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for
nonstandard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields are reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields are
reached. Conventionally this means that the output video will
have corrupted field signals, one generated by the incoming video
and one generated when the internal lines/field counters reach
the end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h,
Bit 5], the lines/field counters are updated according to the
incoming vsync signal, and the analog output matches the incoming
vsync signal.
This control is available in all slave timing modes except
Slave Mode 0.
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