參數(shù)資料
型號(hào)： ADV7330
廠商： Analog Devices, Inc.
英文描述： Multiformat 11-Bit Triple DAC Video Encoder
中文描述： 多格式11位DAC的視頻編碼器三
文件頁(yè)數(shù)： 29/76頁(yè)
文件大小： 1378K
代理商： ADV7330
REV. B
ADV7330
–29–
TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bit 3,2]
For any input data that does not conform to the standards select-
able in input mode, Subaddress 10h, asynchronous timing mode
can be used to interface to the ADV7330. Timing control signals
for Hsync, Vsync, and Blank have to be programmed by the user.
Macrovision and programmable oversampling rates are not avail-
able in async timing mode. In async mode, the PLL must be
turned off [Subaddress 01h, Bit 1 = 1].
CLK
ACTIVE VIDEO
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
a
b
c
d
81
66
66
243
1920
HORIZONTAL SYNC
e
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
SET ADDRESS 10h,
BIT 6 TO 1
Figure 20a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
ACTIVE VIDEO
0
1
HORIZONTAL SYNC
a
b
c
d
e
CLK
HSYNC_I/P
VSYNC_I/P
BLANK_I/P
SET ADDRESS 10h,
BIT 6 TO 1
ANALOG OUTPUT
Figure 20b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signals
Figures 20a and 20b show an example of how to program
the ADV7330 to accept a different high definition standard
other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358.
The following truth table must be followed when programming
the control signals in async timing mode.
For standards that do not require a tri-sync level,
BLANK_I/P
must be tied low at all times.
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