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參數(shù)資料
| 型號(hào)： | ADV7330 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 11-Bit Triple DAC Video Encoder |
| 中文描述： | 多格式11位DAC的視頻編碼器三 |
| 文件頁(yè)數(shù)： | 46/76頁(yè) |
| 文件大小： | 1378K |
| 代理商： | ADV7330 |
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REV. B
–46–
ADV7330
ADAPTIVE FILTER CONTROL APPLICATION
Figures 36 and 37 show a typical signal to be processed by the
adaptive filter control block.
: 692mV
@: 446mV
: 332ns
@: 12.8ms
Figure 36. Input Signal to Adaptive Filter Control
: 692mV
@: 446mV
: 332ns
@: 12.8ms
Figure 37. Output Signal After Adaptive Filter Control
The following register settings were used to obtain the results
shown in Figure 37, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.
Table XIII.
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
10h
20h
00h
81h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
All other registers are set as normal.
When changing the adaptive filter mode to Mode B [Address 15h,
Bit 6], the following output can be obtained:
: 674mV
@: 446mV
: 332ns
@: 12.8ms
Figure 38. Output Signal from Adaptive Filter Control
The adaptive filter control can also be demonstrated using the
internally generated crosshatch test pattern and toggling the
adaptive filter control bit [Address 15h, Bit 7].
Table XIV.
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
10h
20h
00h
85h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
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