參數(shù)資料
型號(hào)： AM79C930VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
中文描述： 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁數(shù)： 120/161頁
文件大?。?/td> 691K
代理商： AM79C930VCW
AMD
P R E L I M I N A R Y
120
Am79C930
TCR26: Reserved
This register is the TAI reserved location register.
CONFIGURATION REGISTER INDEX:
1Ah
Bit
Name
Reset Value
Description
7–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
TCR27: TIP LED Scramble
This register is the Network Interface Polarity register.
This register is used to set the polarity of some of the
transceiver interface output pins.
CONFIGURATION REGISTER INDEX:
1Bh
Bit
Name
Reset Value
Description
7
DISRNR
0
Disable RUNERR. When DISRNR is set to a 1, then the RUNERR
bit of TCR11 will always be held at a 0 value. When DISRNR is set
to a 0, then the RUNERR bit of TCR11 will function as described in
the TCR11 bit description.
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
LNK
pin drive. When set to a 0, the drive of the
LNK
pin will be open
drain. When set to a 1, the drive of the
LNK
pin will be totem pole,
i.e., both high and low output values will be driven.
Complete control of the function of the
LNK
pin is described in the
Multi-Function Pinsection.
ACT
pin drive. When set to a 0, the drive of the
ACT
pin will be open
drain. When set to a 1, the drive of the
ACT
pin will be totem pole,
i.e., both high and low output values will be driven.
Complete control of the function of the
ACT
pin is described in the
Multi-Function Pinsection.
FDET
Polarity. When this bit is set to a 0, then the polarity of the
FDET
output will be low assert, such that when the SFD pattern has
been recognized in the incoming receive data stream or the outgo-
ing transmit data stream, the
FDET
pin will be driven to a LOW logic
level. When this bit is set to a 1, then the polarity of the
FDET
output
will be high assert, such that when the SFD pattern has been recog-
nized in the incoming receive data stream or the outgoing transmit
data stream, the
FDET
pin will be driven to a HIGH logic level.
TXPE
Polarity. When this bit is set to a 0, then the polarity of the
TXPE
output will be low assert, such that when the TGAP1 counter
expires, the
TXPE
pin will be driven to a LOW logic level. When this
bit is set to a 1, then the polarity of the
TXPE
output will be high as-
sert, such that when the TGAP1 counter expires, the
TXPE
pin will
be driven to a HIGH logic level.
TXMOD
Polarity. When this bit is set to a 0, then the polarity of the
TXMOD
output will be low assert, such that when the TGAP2
counter expires, the
TXMOD
pin will be driven to a LOW logic level.
When this bit is set to a 1, then the polarity of the
TXMOD
output will
6
Reserved
–
5
Reserved
0
4
LNKDR
0
3
ACTDR
0
2
FDETPOL
0
1
TXPEPOL
0
0
TXMODPOL
0
相關(guān)PDF資料
PDF描述
AM79C940VCW Media Access Controller for Ethernet (MACE)
AM79C940 Media Access Controller for Ethernet (MACE)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C940 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE)
AM79C940_00 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩)
AM79C940-16/25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
AM79C940-16JC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
AM79C940-25JC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller
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