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參數(shù)資料
| 型號(hào)： | AM79C930VCW |
| 廠(chǎng)商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | PCnet-Mobile Single-Chip Wireless LAN Media Access Controller |
| 中文描述： | 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 16/161頁(yè) |
| 文件大?。?/td> | 691K |
| 代理商： | AM79C930VCW |
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1
6
Am79C930
P R E L I M I N A R Y
PCMCIA PIN FUNCTION SUMMARY
PCMCIA Pin Summary
No. of
Pins
Pin Name
Pin Function
Pin Style
15
A14–A0
PCMCIA address bus lines
I
8
D7–D0
PCMCIA data bus lines
TS2
1
RESET
PCMCIA bus RESET line
I
1
CE1
Card Enable 1—used to enable the D7–0 pins for PCMCIA Read and Write
accesses
I
1
OE
Output Enable—used to enable the output drivers of the Am79C930 device for
PCMCIA Read accesses
I
1
WE
Write Enable—used to indicate that the current PCMCIA cycle is a write access
I
1
REG
REG—used to indicate that the current PCMCIA cycle is to the Attribute
Memory space of the Am79C930 device
I
1
INPACK
Input Acknowledge—used to indicate that the Am79C930 device will respond
to the current I/O read cycle
TS1
1
WAIT
Wait—used to delay the termination of the current PCMCIA cycle
TS2
1
IORD
I/O Read—this signal is asserted by the PCMCIA host system whenever an
I/O read operation occurs
1
IOWR
I/O Write—this signal is asserted by the PCMCIA host system whenever an
I/O write operation occurs
I
1
IREQ
Interrupt Request—this line is asserted when the Am79C930 device needs
servicing from the software
PTS3
1
STSCHG
Status Change—PCMCIA output used only for WAKEUP signaling
PTS1
1
PCMCIA
PCMCIA mode—selects PCMCIA or ISA Plug and Play mode
I
1
PWRDWN
Powerdown—indicates that device is in the power down mode
TP1
17
MA16–0
Memory Address Bus—these lines are used to address locations in the Flash
device, the SRAM device, and an extra peripheral device that are contained
within an Am79C930-based design
TP1
8
MD7–0
Memory Data Bus—these lines are used to write and read data to/from Flash,
SRAM, and/or an extra peripheral device within an Am79C930-based design
TS1
1
FCE
Flash Chip Enable—this signal becomes asserted when the Flash device has
been addressed by either the 80188 core of the Am79C930 device or by the
software through the PCMCIA interface
TP1
1
SCE
SRAM Chip Enable—this signal becomes asserted when the SRAM device
has been addressed by either the 80188 core of the Am79C930 device or by
the software through the PCMCIA interface
TP1
1
XCE
eXtra Chip Enable—this signal becomes asserted when the extra peripheral
device has been addressed by the 80188 core of the Am79C930 device (XCE
is not accessible through the system interface)
TP1
1
MOE
Memory Output Enable—this signal becomes asserted during reads of devices
located on the memory interface bus
TP1
1
MWE
Memory Write Enable—this signal becomes asserted during writes to devices
located on the memory interface bus
TP1
1
TCK
Test Clock—this is the clock signal for IEEE 1149.1 testing
I
1
TDI
Test Data In—this is the data input signal for IEEE 1149.1 testing
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C940VCW | Media Access Controller for Ethernet (MACE) |
| AM79C940 | Media Access Controller for Ethernet (MACE) |
| AM79C940JCW | Media Access Controller for Ethernet (MACE) |
| AM79C940KCW | Media Access Controller for Ethernet (MACE) |
| AM79C960 | PCnetTM-ISA Single-Chip Ethernet Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C940 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE) |
| AM79C940_00 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Media Access Controller for Ethernet (MACE⑩) |
| AM79C940-16/25 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述: |
| AM79C940-16JC | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:LAN Node Controller |
| AM79C940-25JC | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:LAN Node Controller |
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