參數(shù)資料
型號(hào): AM79C930VCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: PCnet-Mobile Single-Chip Wireless LAN Media Access Controller
中文描述: 2 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: TQFP-144
文件頁數(shù): 133/161頁
文件大小: 691K
代理商: AM79C930VCW
P R E L I M I N A R Y
AMD
133
Am79C930
PCMCIA I/O READ ACCESS
Parameter
Symbol
t
AVIGL
t
IGHAX
t
RGLIGL
t
IGHRGH
t
ELIGL
t
IGHEH
t
IGLIGH
t
IGLIAL
t
IGHIAH
t
IGLWTL
t
WTLWTH
t
WTHQV
t
IGLQNZ
t
IGLQV
t
IGHQX
t
IGHQZ
Parameter Description
Address setup to
IORD
Address hold from
IORD
REG
setup to
IORD
REG
hold from
IORD
CE
setup to
IORD
CE
hold from
IORD
IORD
width
INPACK
delay from
IORD
INPACK
delay from
IORD
WAIT
delay from
IORD
WAIT
width
Data delay from
WAIT
Data enabled from
IORD
Data delay from
IORD
Data hold from
IORD
Data disabled from
IORD
Test Conditions
Min
70
20
5
0
5
20
165
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
45
35
Notes 1, 2
53 X T
CLKIN
0
Note 2
0
100
0
Note 2
20
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
FLASH and SRAM wait states set at “3.”
1
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle s posted nternal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
4
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
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