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參數(shù)資料
| 型號(hào)： | AM79C970AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13 |
| 封裝： | CARRIER RING, PLASTIC, QFP-132 |
| 文件頁數(shù)： | 25/219頁 |
| 文件大?。?/td> | 1065K |
| 代理商： | AM79C970AKC |
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P R E L I M I N A R Y
AMD
25
Am79C970A
will be ignored except for the
SLEEP
pin itself. Deasser-
tion of
SLEEP
results in wake-up. The system must re-
frain from starting the network operations of the
PCnet-PCI II controller device for 0.5 s following the
deassertion of the
SLEEP
signal in order to allow inter-
nal analog circuits to stabilize.
Both CLK and XTAL1 inputs must have valid clock sig-
nals present in order for the
SLEEP
command to
take effect.
The
SLEEP
pin should not be asserted during power
supply ramp-up. If it is desired that
SLEEP
be asserted
at power up time, then the system must delay the asser-
tion of
SLEEP
until three clock cycles after the comple-
tion of a hardware reset operation.
The
SLEEP
pin must not be left unconnected. It should
be tied to VDD, if the power savings mode is not used.
XTAL1
Crystal Oscillator In
The internal clock generator uses a 20 MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the crystal frequency. XTAL1
may alternatively be driven using an external 20 MHz
CMOS level clock signal. Refer to the section “External
Crystal Characteristics” for more details.
Input
Note that when the PCnet-PCI II controller is in coma
mode, there is an internal 22 k
resistor from XTAL1 to
ground. If an external source drives XTAL1, some
power will be consumed driving this resistor. If XTAL1 is
driven LOW at this time power consumption will be mini-
mized. In this case, XTAL1 must remain active for at
least 30 cycles after the assertion of
SLEEP
and
deassertion of
REQ
.
XTAL2
Crystal Oscillator Out
The internal clock generator uses a 20 MHz crystal that
is attached to the pins XTAL1 and XTAL2. The network
data rate is one-half of the crystal frequency. If an exter-
nal clock source is used on XTAL1, then XTAL 2 should
be left unconnected.
Output
Microwire EEPROM Interface
EECS
EEPROM Chip Select
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EECS is connected to the Microwire EEPROM chip se-
lect pin. It is controlled by either the PCnet-PCI II con-
troller during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 2.
Output
EEDI
EEPROM Data In
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EEDI is connected to the Microwire EEPROM data input
pin. It is controlled by either the PCnet-PCI II controller
during command portions of a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 0.
Output
Note that the EEDI pin is multiplexed with the
LNKST
pin.
EEDO
EEPROM Data Out
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EEDO is connected to the Microwire EEPROM data out-
put pin. It is controlled by either the PCnet-PCI II control-
ler during command portions of a read of the entire
EEPROM, or indirectly by the host system by reading
from BCR19, bit 0.
Input
Note that the EEDO pin is multiplexed with the
LED3
and SRD pins.
EESK
EEPROM Serial clock
This pin is designed to directly interface to a serial
EEPROM that uses the Microwire interface protocol.
EESK is connected to the Microwire EEPROM clock pin.
It is controlled by either the PCnet-PCI II controller di-
rectly during a read of the entire EEPROM, or indirectly
by the host system by writing to BCR19, bit 1.
Input/Output
Note that the EESK pin is multiplexed with the
LED1
and
SFBD pins.
The EESK pin is also used during EEPROM Auto-detec-
tion to determine whether or not an EEPROM is present
at the PCnet-PCI II controller Microwire interface. At the
rising edge of CLK during the last clock during which
RST
is asserted, EESK is sampled to determine the
value of the EEDET bit in BCR19. A sampled HIGH
value means that an EEPROM is present, and EEDET
will be set to ONE. A sampled LOW value means that an
EEPROM is not present, and EEDET will be cleared to
ZERO. See the section “EEPROM Auto-Detection” for
more details.
If no LED circuit is to be attached to this pin, then a pull
up or pull down resistor must be attached instead, in or-
der to resolve the EEDET setting.
相關(guān)PDF資料 |
PDF描述 |
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| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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