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參數(shù)資料
| 型號(hào)： | AM79C970AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13 |
| 封裝： | CARRIER RING, PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 86/219頁(yè) |
| 文件大小： | 1065K |
| 代理商： | AM79C970AKC |
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AMD
P R E L I M I N A R Y
86
Am79C970A
Multipair cables within the same outer sheath have
lower crosstalk attenuation, and may allow noise emit-
ted from adjacent pairs to couple into the receive pair,
and be of sufficient amplitude to falsely unsquelch
the T-MAU.
Link Test Function
The Link Test Function is implemented as specified by
the 10BASE-T standard. During periods of transmit pair
inactivity, “Link beat pulses” will be periodically sent
over the twisted pair medium to constantly monitor
medium integrity.
When the link test function is enabled (DLNKTST bit in
CSR15 is cleared), the absence of link beat pulses and
receive data on the RXD
±
pair will cause the T-MAU to
go into a Link Fail state. In the Link Fail state, data trans-
mission, data reception, data loopback and the collision
detection functions are disabled, and remain disabled
until valid data or more than five consecutive link pulses
appear on the RXD
±
pair. During Link Fail, the Link
Status signal is inactive. When the link is identified as
functional, the Link Status signal is asserted. The
LNKST
pin displays the Link Status signal by default.
The T-MAU will power up in the Link Fail state and the
normal algorithm will apply to allow it to enter the Link
Pass state. If T-MAU is selected using the PORTSEL
bits in CSR15, the T-MAU will be forced into the Link Fail
state when moving from AUI to T-MAU selection.
Transmission attempts during Link Fail state will pro-
duce no network activity and will produce LCAR and
CERR error indications.
In order to interoperate with systems which do not imple-
ment Link Test, this function can be disabled by setting
the DLNKTST bit in CSR15. With link test disabled, the
data driver, receiver and loopback functions as well as
collision detection remain enabled irrespective of the
presence or absence of data or link pulses on the RXD
±
pair. Link Test pulses continue to be sent regardless of
the state of the DLNKTST bit.
Polarity Detection and Reversal
The T-MAU receive function includes the ability to invert
the polarity of the signals appearing at the RXD
±
pair if
the polarity of the received signal is reversed (such as in
the case of a wiring error). This feature allows data
frames received from a reverse wired RXD
±
input pair to
be corrected in the T-MAU prior to transfer to the
MENDEC. The polarity detection function is activated
following H_RESET or Link Fail, and will reverse the re-
ceive polarity based on both the polarity of any previous
link beat pulses and the polarity of subsequent frames
with a valid End Transmit Delimiter (ETD).
When in the Link Fail state, the T-MAU will recognize
link beat pulses of either positive or negative polarity.
Exit from the Link Fail state is made due to the reception
of 5–6 consecutive link beat pulses of identical polarity.
On entry to the Link Pass state, the polarity of the last 5
link beat pulses is used to determine the initial receive
polarity configuration and the receiver is reconfigured to
subsequently recognize only link beat pulses of the pre-
viously recognized polarity.
Positive link beat pulses are defined as received signal
with a positive amplitude greater than 585 mV (LRT = 1)
with a pulse width of 60 ns–200 ns. This positive excur-
sion may be followed by a negative excursion. This defi-
nition is consistent with the expected received signal at
a correctly wired receiver, when a link beat pulse which
fits the template of Figure 14-12 of the 10BASE-T Stan-
dard is generated at a transmitter and passed through
100 m of twisted pair cable.
Negative link beat pulses are defined as received sig-
nals with a negative amplitude greater than 585 mV with
a pulse width of 60–200 ns. This negative excursion
may be followed by a positive excursion. This definition
is consistent with the expected received signal at a re-
verse wired receiver, when a link beat pulse which fits
the template of Figure 14-12 in the 10BASE-T Standard
is generated at a transmitter and passed through 100 m
of twisted pair cable.
The polarity detection/correction algorithm will remain
“armed” until two consecutive frames with valid ETD of
identical polarity are detected. When “armed”, the re-
ceiver is capable of changing the initial or previous po-
larity configuration based on the ETD polarity.
On receipt of the first frame with valid ETD following
H_RESET or Link Fail, the T-MAU will utilize the
inferred polarity information to configure its RXD
±
input,
regardless of its previous state. On receipt of a second
frame with a valid ETD with correct polarity, the
detection/correction algorithm will “l(fā)ock-in” the received
polarity. If the second (or subsequent) frame is not de-
tected as confirming the previous polarity decision, the
most recently detected ETD polarity will be used as the
default. Note that frames with invalid ETD have no effect
on updating the previous polarity decision. Once two
consecutive frames with valid ETD have been received,
the T-MAU will disable the detection/correction
algorithm until either a Link Fail condition occurs or
H_RESET is activated.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when
enabled by the LED control bits in the Bus Configuration
Registers (BCR4 to BCR7).
Twisted Pair Interface Status
When the T-MAU is in Link Pass state, three signals
(XMT, RCV and COL) indicate whether the T-MAU is
相關(guān)PDF資料 |
PDF描述 |
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| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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