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參數(shù)資料
| 型號(hào)： | AM79C970AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13 |
| 封裝： | CARRIER RING, PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 34/219頁(yè) |
| 文件大小： | 1065K |
| 代理商： | AM79C970AKC |
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AMD
P R E L I M I N A R Y
34
Am79C970A
19436A-7
FRAME
CLK
AD
IRDY
TRDY
C/
BE
DEVSEL
STOP
PAR
ADDR
0111
PAR
1
2
3
4
5
6
7
8
10
9
11
DATA
PAR
BE
Figure 4. Slave Write Using Memory Command
Expansion ROM Transfers
The host must initialize the Expansion ROM Base Ad-
dress register at offset 30h in the PCI configuration
space with a valid address before enabling the access to
the device. The base address must be aligned to a 64K
boundary as indicated by ROMSIZE (PCI Expansion
ROM Base Address register, bits 15–11). The
PCnet-PCI II controller will not react to any access to the
Expansion ROM until both MEMEN (PCI Command reg-
ister, bit 1) and ROMEN (PCI Expansion ROM Base Ad-
dress register, bit 0) are set to ONE. After the Expansion
ROM is enabled, the PCnet-PCI II controller will assert
DEVSEL
on all memory read accesses with an address
between ROMBASE and ROMBASE + 64K – 4. The
PCnet-PCI II controller aliases all accesses to the Ex-
pansion ROM of the command types “Memory Read
Multiple” and “Memory Read Line” to the basic Memory
Read command. Eight-bit, 16-bit and 32-bit read trans-
fers are supported.
Since setting MEMEN also enables memory mapped
access to the I/O resources, attention must be given the
PCI Memory Mapped I/O Base Address register, before
enabling access to the Expansion ROM. The host must
set the PCI Memory Mapped I/O Base Address register
to a value that prevents the PCnet-PCI II controller from
claiming any memory cycles not intended for it.
The PCnet-PCI II controller will always read four bytes
for every host Expansion ROM read access.
TRDY
will
not be asserted until all four bytes are loaded into an in-
ternal scratch register. The cycle
TRDY
is asserted de-
pends on the programming of the Expansion ROM
interface timing. The following figure assumes that
ROMTMG (BCR18, bits 15–12) is at its default value.
Since the target latency for the Expansion ROM access
is considerably long, the PCnet-PCI II controller discon-
nects at the second data phase, when the host tries do
to perform a burst read operation of the Expansion
ROM. This behavior complies with the requirements for
latency issues in the PCI environment and allows other
devices to get fair access to the bus.
When the host tries to write to the Expansion ROM, the
PCnet-PCI II controller will claim the cycle by asserting
DEVSEL
.
TRDY
will be asserted one clock cycle later.
The write operation will have no effect.
The PCnet-PCI II controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register,
相關(guān)PDF資料 |
PDF描述 |
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| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
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