參數(shù)資料
型號(hào)： AM79C976KIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 177/309頁(yè)
文件大?。?/td> 2070K
代理商： AM79C976KIW
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8/01/00
Am79C976
177
P R E L I M I N A R Y
generated when the
header
bytes
have been written to the
header
memory area.
Read/Write accessible. The LAP-
PEN bit will be reset to 0 by
H_RESET or S_RESET and will
be unaffected by STOP.
See Appendix B for more infor-
mation on the Look Ahead Pack-
et Processing concept.
4
DXMT2PD
Disable Transmit Two Part Defer-
ral (see Medium Allocation sec-
tion
in
the
Management
section for more
details). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
Media
Access
Read/Write
DXMT2PD
H_RESET or S_RESET and is
not affected by STOP.
accessible.
cleared
is
by
3
EMBA
Enable Modified Back-off Algo-
rithm (see Contention Resolution
section in
Media Access Man-
agement
section for more de-
tails). If EMBA is set, a modified
back-off algorithm is implement-
ed.
Read/Write accessible. EMBA is
cleared
by
S_RESET and is not affected by
STOP.
H_RESET
or
2
BSWP
Byte Swap. This bit is used to
choose between big and little En-
dian modes of operation. When
BSWP is set to a 1, big Endian
mode is selected. When BSWP is
set to 0, little Endian mode is se-
lected.
When big Endian mode is select-
ed, the Am79C976 controller will
swap the order of bytes on the AD
bus during a data phase on ac-
cesses to the FIFOs only. Specif-
ically, AD[31:24] becomes Byte
0, AD[23:16] becomes Byte 1,
AD[15:8] becomes Byte 2, and
AD[7:0] becomes Byte 3 when
big Endian mode is selected.
When little Endian mode is se-
lected, the order of bytes on the
AD bus during a data phase is:
AD[31:24] is Byte 3, AD[23:16] is
Byte 2, AD[15:8] is Byte 1, and
AD[7:0] is Byte 0.
Byte swap only affects data
transfers that involve the FIFOs.
Initialization block transfers are
not affected by the setting of the
BSWP bit. Descriptor transfers
are not affected by the setting of
the BSWP bit. RDP, RAP, BDP
and PCI configuration space ac-
cesses are not affected by the
setting of the BSWP bit. Address
PROM transfers are not affected
by the setting of the BSWP bit.
Expansion ROM accesses are
not affected by the setting of the
BSWP bit.
Note that the byte ordering of the
PCI bus is defined to be little En-
dian. BSWP should not be set to
1 when the Am79C976 controller
is used in a PCI bus application.
Read/Write accessible. BSWP is
cleared
by
S_RESET and is not affected by
STOP.
H_RESET
or
1-0
RES
Reserved locations. The values
written to these bits have no ef-
fect on the operation of the de-
vice. These bits should be read
as undefined.
"
Certain bits in CSR4 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR4 and write back
the value just read to clear the interrupt condition.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
RES
Reserved location. The value
written to this bit has no effect on
the operation of the device. This
bit should be read as undefined.
14
DMAPLUS
Writing and reading from this bit
has no effect. DMAPLUS is al-
ways 0.
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