參數(shù)資料
型號(hào)： AM79C976KIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 224/309頁(yè)
文件大?。?/td> 2070K
代理商： AM79C976KIW
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224
Am79C976
8/01/00
P R E L I M I N A R Y
H_RESET, and is unaffected by
S_RESET and the STOP bit.
7
PMAT_MODE
Pattern Match Mode. Writing a 1
to this bit will enable Pattern
Match Mode and should only be
done after the Pattern Match
RAM has been programmed.
Read and write accessible.
PMAT_MODE is reset to 0 when
power is initially applied to the de-
vice, and is unaffected by
S_RESET and the STOP bit.
6-0
PMR_ADDR Pattern Match Ram Address.
These bits are the Pattern Match
Ram address to be written to or
read from.
Read and write accessible.
PMR_ADDR is reset to 0 when
power is first applied to the de-
vice (after power-on reset), and is
unaffected
by
S_RESET and the STOP bit.
H_RESET,
",80#(+
Note:
This register is used to control and indirectly ac-
cess the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the ad-
dress of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to what-
ever PMR word is addressed by bits 6:0 of BCR45.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-8
PMR_B2
Pattern Match RAM Byte 2. This
byte is written into or read from
Byte 2 of the Pattern Match RAM.
Read and write accessible.
PMR_B2 is undefined after
H_RESET, and is unaffected by
S_RESET and the STOP bit.
7-0
PMR_B1
Pattern Match RAM Byte 1. This
byte is written into or read from
Byte 1 of Pattern Match RAM.
Read and write accessible.
PMR_B1 is undefined after
H_RESET, and is unaffected by
S_RESET and the STOP bit.
"/80#(+
Note:
This register is used to control and indirectly ac-
cess the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the ad-
dress of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to what-
ever PMR word is addressed by bits 6:0 of BCR45.
When PMAT_MODE is 0, the contents of the word ad-
dressed by bits 6:0 of BCR45 can be read by reading
BCR45-47 in any order.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-8
PMR_B4
Pattern Match RAM Byte 4. This
byte is written into or read from
Byte 4 of Pattern Match RAM.
Read and write accessible.
PMR_B4 is undefined after
H_RESET, and is unaffected by
S_RESET and the STOP bit.
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