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參數(shù)資料
| 型號(hào)： | AM79C976KIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 84/309頁(yè) |
| 文件大?。?/td> | 2070K |
| 代理商： | AM79C976KIW |
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84
Am79C976
8/01/00
P R E L I M I N A R Y
To generate a non-blocking read from a PHY register
the host CPU specifies the address of the external PHY
device in the PHY_ADDR field and the PHY register
number in the PHY_REG_ADDR field of the PHY Ac-
cess Register and sets the PHY_NBLK_RD_CMD bit.
The host CPU can then poll the register until the
PHY_CMD_DONE bit is 1, or it can wait for the MII
Management Command Complete Interrupt (MCCINT
in the Int0 Register). When the PHY_CMD_DONE bit
is 1, the PHY_DATA field contains the data read from
the specified external PHY register. If an error occurs in
the read operation, the MII Management Read Error In-
terrupt (MREINT) bit in the Interrupt0 Register is set,
and if the corresponding enable bit is set (MREINTE in
the Interrupt Enable Register), the host CPU is inter-
rupted.
To generate a blocking read, the host CPU uses the
same procedure as it does for a non-blocking read, ex-
cept that it sets the PHY_BLK_RD_CMD bit rather than
the PHY_NBLK_RD_CMD bit, and it can poll the PHY
Access Register until the PHY_CMD_DONE bit is set.
The host CPU must not set both the
PHY_BLK_RD_CMD bit and the PHY_NBLK_RD_CMD
bit at the same time.
The host CPU must not attempt a second PHY register
access until the first access is complete. When the ac-
cess is complete, the PHY_CMD_DONE bit in the PHY
Access Register and the MII Management Command
Complete Interrupt (MCCINT) bit in the Interrupt Reg-
ister will be set to 1, and if the corresponding enable bit
is set, the host CPU will be interrupted. The host can
either wait for this interrupt, or it can use some other
method to guarantee that it waits for a long enough
time. Note that with a 2.5 MHz MDC clock it takes about
27 μs to transmit a management frame with a pream-
ble. However, if the Auto-Poll or Port Manager ma-
chines are active, there may be a delay in sending a
host generated management frame while other frames
are sent. Under these conditions, the host should al-
ways check for command completion.
For an MII Management Frame transmitted as the re-
sult of a host CPU access to the PHY Access Register,
preamble suppression is controlled by the Preamble
Suppression bit (PRE_SUP) in the PHY Access Regis-
ter. If this bit is set to 1 the preamble will be sup-
pressed. Otherwise, the frame will include a preamble.
The host CPU should only set the Preamble Suppres-
sion bit when accessing a register in a PHY device that
is known to be able to accept management frames
without preambles. For PHY devices that comply with
Clause 22 of IEEE Std 802.3, bit 6 of PHY Register 1 is
fixed at 1 if the PHY will accept management frames
with the preamble suppressed.
MII Management Frames transmitted as the result of a
host CPU accesses to the legacy BCR33 and BCR34
registers are always sent with preambles.
See
Appendix B, MII Management Registers,
for de-
scriptions of the standard registers that are found in
IEEE 802.3 compatible devices.
-0#(+
As defined in the IEEE 802.3 standard, the external
PHY attached to the Am79C976 controller
’
s MII has no
way of communicating important timely status informa-
tion back to the Am79C976 controller. Unless it polls
the external PHY
’
s status register, the Am79C976 con-
troller has no way of knowing that an external PHY has
undergone a change in status. Although it is possible
for the host CPU to poll registers in external PHY de-
vices, the Am79C976 controller simplifies this process
by implementing an automatic polling function that pe-
riodically polls up to 6 user-selected PHY registers and
interrupts the host CPU if the contents of any of these
registers change.
The automatic polling of PHY registers is controlled by
six 16-bit Auto-Poll registers, AUTOPOLL0 to
AUTOPOLL5. By writing to the Auto-Poll registers, the
user can independently define the PHY addresses and
register numbers for six external PHY registers. The
registers are not restricted to a single PHY device. In
the Auto-Poll registers there is an enable bit for each of
the selected PHY registers. When the host CPU sets
one of these enable bits, the Auto-Poll logic reads the
corresponding PHY register and stores the result in the
corresponding Auto-Poll Data Register. (There is one
Auto-Poll Data register for each of the six PHY regis-
ters.) Thereafter, at each polling interval, the Auto-Poll
logic compares the current contents of the selected
PHY register with the corresponding Auto-Poll Data
Register. If it detects a change, it sets the MII Manage-
ment Auto-Poll Interrupt (MAPINT) in the Interrupt Reg-
ister, which causes an interrupt to the host CPU (if that
interrupt is enabled).
Note that when the host CPU writes to one of the Auto-
Poll Registers the contents of the associated Auto-Poll
Data Register are considered to be invalid during the
next polling cycle so that the next polling cycle updates
the appropriate Auto-Poll Data Register without caus-
ing an interrupt.
When the contents of one of the selected PHY regis-
ters changes, the corresponding Auto-Poll Data Regis-
ter is updated so that another interrupt will occur when
the data changes again.
Auto-Poll Register 0 differs from the other Auto-Poll
Registers in several ways. The PHY address
(AP_PHY0_ADDR) field of this register defines the de-
fault PHY address that is used by both the Auto-Poll
State Machine and the Network Port Manager. The
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