218
Am79C976
8/01/00
P R E L I M I N A R Y
MIIPD is read only. Write opera-
tions are ignored.
13-12
FMDC
Fast Management Data Clock.
When FMDC is set to 2h the MII
Management Data Clock will run
at 10 MHz max. The Manage-
ment Data Clock will no longer be
IEEE 802.3u-compliant and set-
ting this bit should be used with
care. The accompanying external
PHY must also be able to accept
management frames at the new
clock rate. When FMDC is set to
1h, the MII Management Data
Clock will run at 5 MHz max. The
Management Data Clock will no
longer be IEEE 802.3u-compliant
and setting this bit should be
used with care. The accompany-
ing external PHY must also be
able to accept management
frames at the new clock rate.
When FMDC is set to 0h, the MII
Management Data Clock will run
at 2.5 MHz max and will be fully
compliant to IEEE 802.3u stan-
dards. See Table 94.
Read/Write accessible. FMDC is
set to 0 during H_RESET, and is
unaffected by S_RESET and the
STOP bit
11
APEP
MII Auto-Poll External PHY.
when APEP is set to 1, the
Am79C976 controller will poll the
MII status register in the external
PHY. This feature allows the soft-
ware driver or upper layers to see
any changes in the status of the
external PHY. An interrupt, when
enabled, is generated when the
contents of the new status is dif-
ferent from the previous status.
Read/Write accessible. APEP is
set to 0 during H_RESET and is
unaffected by S_RESET and the
STOP bit.
10-8
APDW
MII Auto-Poll Dwell Time. APDW
determines the dwell time be-
tween MII Management Frames
accesses
when
turned on. See Table 95.
Auto-Poll
is
Read/Write accessible. APDW is
set to 100b after H_RESET and
is unaffected by S_RESET and
the STOP bit.
7
DISPM
Disable Port Manager. (The cor-
responding bit in older PCnet
family devices is called Disable
Auto-Negotiation Auto Setup or
DANAS. The name has been
changed, but not the function.)
When
Am79C976 controller after a
H_RESET or S_RESET will re-
main dormant and not automati-
cally
start
up
Negotiation section or the en-
hanced automatic port selection
section. Instead, the Am79C976
controller will wait for the soft-
ware driver to set up the Auto-Ne-
gotiation portions of the device.
The MII programming in BCR33
and BCR34 is still valid. The
Am79C976 controller will not
generate
any
frames unless Auto-Poll is en-
abled.
DISPM
is
set,
the
the
Auto-
management
Read/write accessible. DISPM is
set to 0 by H_RESET and is unaf-
fected by S_RESET and the
STOP bit.
6
XPHYRST
External PHY Reset. When XPH-
YRST is set, the Am79C976 con-
troller after an H_RESET or
S_RESET will issue an MII man-
agement frame that will reset the
Table 94. FMDC Values
Fast Management Data Clock
2.5 MHz max
5 MHz max
10 MHz max
Reserved
FMDC
00
01
10
11
Table 95. APDW Values
Auto-Poll Dwell Time
Continuous (26 s @ 2.5 MHz)
Every 64 MDC cycles (51 s @ 2.5 MHz)
Every 128 MDC cycles (103 s @ 2.5 MHz)
Every 256 MDC cycles (206 s @ 2.5 MHz)
Every 512 MDC cycles (410 s @ 2.5 MHz)
Every 1024 MDC cycles (819 s @ 2.5 MHz)
Reserved
APDW
000
001
010
011
100
101
110-111