參數(shù)資料
型號: AS3543-ECTP
廠商: ams
文件頁數(shù): 41/92頁
文件大?。?/td> 0K
描述: IC CODEC AUDIO FRONT END 68CTBGA
標準包裝: 4,000
類型: 音頻編解碼器
應用: 便攜式音頻,電話
安裝類型: 表面貼裝
封裝/外殼: 68-TFBGA
供應商設備封裝: 68-CTBGA(6x6)
包裝: 帶卷 (TR)
www.austriamicrosystems.com
Revision 1.11
45 - 91
AS3543 3v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
10.1.5 Register Description
10.2
Hibernation
10.2.1 General
Hibernation allows shutting down a part or the complete system. Hibernation can be terminated by every possible
interrupt of the AFE. E.g. one can use the RTC for a time triggered wake-up. The interrupt has to be enabled before
going to hibernation.:
10.2.2 Register Description
Table 31. System Related Register
Name
Base
Offset
Description
2-wire serial
1A-1h
Control of PWGD and XRES signal and drive
2-wire serial
1A-4h
Selection of HBT input pin
2-wire serial
1Ch
Enables writings to extended registers 1Ah-1 and 1Ah-5
2-wire serial
20h
Watchdog and Over-temperature control, Power down enable
2-wire serial
21h
Set emergency shutdown time
2-wire serial
23h
Enable/disable PMU interrupts
2-wire serial
24h
Enable/disable wake-up, voice and PMU interrupts
2-wire serial
25h
Enable/disable charger, USB and supervisor interrupts
2-wire serial
26h
Enable/disable junction temperature interrupt
Table 32. Hibernation
State
Description
Enter
To enter hibernation mode the following settings have to be done:
- Enable just these IRQ sources which should lead to leave hibernation mode.
- Make sure that IRQ is inactive (IRQ flags get cleared by Reg0x23-27 readings.
- Define which regulators should be kept powered and enter hibernation by writing to Reg
1Ch_0x06 + Reg 17h_0xXX
Note that hibernation will shutdown regulators which are not in the keep list of the mentioned
Reg 17h writing and which are powered by the selected power-up sequence.
(e.g. PVDD2 will not go hibernation with VPRG3 is vss or vdd)
Hibernation
VDD27 chip supply is kept ON
All other regulators are switched OFF dependent on the KEEP-Bits
XRES goes active and PWGD goes inactive.
Leave
The chip will come out of Hibernation with IRQ activation.
Start-Up sequence is provided defined by the VPRG state latched on the previous Start-Up.
(VPRG state does not get latched again by leaving hibernation)
Table 33. Hibernation Related Register
Name
Base
Offset
Description
2-wire serial
17h-6
Hibernation control
2-wire serial
1Ch
Enables writings to extended register 17h-6
ams
AG
Technical
content
still
valid
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