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參數(shù)資料
| 型號(hào)： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁數(shù)： | 48/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應(yīng)用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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Revision 1.11
51 - 91
AS3543 3v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
XRES Pin
Can drive CLK32K, CLKINT1 or the PWM signal as auxiliary function. The output can be configured to operate in push/
pull (2 different driver strengths) open-drain mode or to be trie-state.
The XRES signal can be delayed by using a capacitor on PWGD pin. Please refer to chapter XRES delay with PWGD
Q24M Pin
Can drive CLKINT1, CLKINT2 or the PWM signal as auxiliary function. The output can be configured to operate in
push/pull (3 different driver strengths) or to be trie-state. It can be used as an input for a heartbeat or external dimming
signal.
Q32K Pin
Can drive CLKINT1, CLKINT2 or the PWM signal as auxiliary function. The output can be configured to operate in
push/pull (3 different driver strengths) or to be trie-state. It can be used as an input for a heartbeat or external dimming
signal.
XIRQ Pin
Can drive CLKINT1, CLKINT2 signal as auxiliary function. The output can be configured to operate in push/pull (2 dif-
ferent driver strengths) open-drain mode or to be trie-state. The interrupt signal polarity can be defined as active-low or
active-high.
SDO Pin
Can drive CLK24M, CLKINT1 or the PWM signal as auxiliary function. The output can be configured to operate in
push/pull (3 different driver strengths) or to be trie-state.
10.7.4 Register Description
10.8
12-24MHz Oscillator
10.8.1 General
This oscillator can be used to generate a system clock for e.g. a microprocessor if needed. It is not needed for any
other AFE function. As the oscillator is default ON, it has to be disabled if not needed.
10.8.2 Register Description
Table 40. GPIO Related Register
Name
Base
Offset
Description
2-wire serial
1A-1h
Control of PWGD and XRES signal and drive
2-wire serial
1A-2h
Control of Q32K signal and drive
2-wire serial
1A-3h
Control of XIRQ signal, polarity and drive
2-wire serial
1A-4h
Selection of HBT and DCDC 15 dimming input pin
2-wire serial
1A-5h
Selection of clock source or drive level for GPIO pins
2-wire serial
1A-6h
PWM duty cycle and polarity settings
2-wire serial
1Ch
Enables writings to extended registers 1Ah-1 to 1Ah-6
Table 41. 12-24MHz Oscillator Related Register
Name
Base
Offset
Description
2-wire serial
1A-5h
Enable/disable oscillator and clock divider settings
2-wire serial
1Ch
Enables writings to extended registers A1Ah-5
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content
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