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Revision 1.11
64 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 56. AudioSet2 Register
Name
Base
Default
AudioSet2
2-wire serial
00h
Offset: 15h
Second Audio Set Register
Control of various audio blocks. This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7
BIAS_OFF
0
R/W
Power-down of the AGND bias if only digital data transfer and
PMU functions are used.
0: bias enabled
1: bias disabled, for power saving in non audio mode
6
SUM_OFF
0
R/W
0: Mixer stage enabled
1: Mixer stage powered down
5
SUM_AGC_OFF
0
R/W
Switches the signal limiter OFF (N20/N21)
0: automatic gain control for summing stage enabled
1: automatic gain control for summing stage disabled
4
SUM_HP_HIQ
0
R/W
0: mixer and headphone stage in low power mode
1: mixer and headphone stage in high quality mode
3:2
GAIN_STEP<1:0>
00
R/W
Sets the transition time of the auto fading for the output stage
00: 2ms/step
01: 4ms/step
10: 8ms/step
11: auto fading off
1:0
VMICS<1:0>
00
R/W
Sets the microphone supply output voltage
00: AVDD17*20/17
01: AVDD17*20/22
10: AVDD17*20/27
11: AVDD17*20/32
Table 57. AudioSet3 Register
Name
Base
Default
AudioSet3
2-wire serial
00h
Offset: 16h
Third Audio Set Register
Control of mixer stage inputs and headphone. This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7
-
0
n/a
6
MICMIX_OFF
0
R/W
0: microphone input to ΣR and ΣL (N12/N13) on
1: microphone input to mixer disabled
5
-
0
n/a
4
ADCMIX_ON
0
R/W
0: ADC input to mixer disabled
1: ADC input to ΣR and ΣL (N12/N13) on
3
LINMIX_OFF
0
R/W
0: line input to ΣR and ΣL (N12/N13) on
1: line input to mixer disabled
2
HP_FASTSTART
0
R/W
0: normal operation
1: shortens delay for start-up when using 220nF on HPGND
1
HP_BIAS
0
R/W
0: 100%
1: 150%, increased bisas for lower noise and THD
0
HPCM_ON
0
R/W
0: headphone common mode buffer is switched off
1: headphone common mode buffer is powerd up
ams
AG
Technical
content
still
valid