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參數(shù)資料
| 型號(hào)： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁(yè)數(shù)： | 80/92頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應(yīng)用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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www.austriamicrosystems.com
Revision 1.11
80 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 83. Second Interrupt Register
Name
Base
Default
IRQENRD_1
2-wire serial
00h
Offset: 24h
Second Interrupt Register
Please be aware that writing to this register will enable/disable the
corresponding interrupts, while reading gets the actual interrupt status and
will clear the register at the same time. It is not possible to read back the
interrupt enable/disable settings. This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7
PWRUP_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at
the PWRUP input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. BVDD/3 at the
PWRUP input pin occurs (PWRUP pin is commonly connected
to the power-up button)
6
WAKEUP_IRQ
0
W
Enables interrupt which is invoked whenever a wake-up from
RTC wake-up counter occurs
0: disable
1: enable
x
R
This bit is set when a wake-up has been invoked by the RTC
wake-up counter.
5
MCLK_IRQ
0
W
Enables interrupt which is invoked whenever a high signal at
the MCLK input pin occurs
0: disable
1: enable
x
R
This bit is set whenever a high level of min. BVDD/3 at the
MCLK input pin occurs (MCLK pin can be used as alternative
power-up button)
4:2
-
0
n/a
1
CVDD2_SD
0
W
Invokes shut-down of AFE when a –10% under-voltage spike
at CVDD2 occurs
0: disable
1: enable
CVDD2_under
x
R
This bit is set when a –5% under-voltage at CVDD2 occurs
0
CVDD2_IRQ
0
W
Enables interrupt for over-voltage/under-voltage supervision of
CVDD2
0: disable
1: enable
CVDD2_over
x
R
This bit is set when a +8% over-voltage at CVDD2 occurs
ams
AG
Technical
content
still
valid
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