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Revision 1.11
70 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 67. CHGVBUS2 Register
Name
Base
Default
CHGVBUS2
2-wire serial
00h
Offset: 19h-2
Charger / VBUS 2 Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7:6
VBUS_COMP_TH
<1:0>
00
R/W
Sets the threshold for the VBUS comparator. The output can
be read in register 25h.
00: 4.5V
01: 3.18V
10: 1.5V
11: 0.6V
5:3
-
000
n/a
-
2
BAT_TEMP
0
R/W
Selects the battery temperature supervision level
0: 0.4/0.5V equal to 55/50°C with 100k NTC
1: 0.6/0.7V equal to 45/42°C with 100k NTC
1:0
CHG_EOC_TH<1:0>
00
R/W
Setes the threshold for the charger EOC (end of charge)
interrupt as a ratio of the constant current (CC) setting.
00: 10% CC
01: 30% CC
10: 50% CC
11: 70% CC
Table 68. Out_Cntr1 Register
Name
Base
Default
Out_Cntr1
2-wire serial
00h
Offset: 1Ah-1
PWGD and XRES Output Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7:6
DRIVE_PWGD<1:0>
00
R/W
Sets the PWGD output pin to open-drain, push-pull or tri-state
and sets various driving strengths
00: 6mA open-drain output
01: 6mA push-pull output
10: 1mA push-pull output
11: HiZ, stri-state
5:4
MUX_PWGD<1:0>
00
R/W
Multiplexes various digital signals to the PWGD output pin
00: PWGD, PowerGood control signal
01: CLK24M, 24MHz oszillator output
10: CLKINT2, internal clock signal, see Clk_Cntr regsiter
11: PWM, PMW_Cntr register
ams
AG
Technical
content
still
valid