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參數(shù)資料
| 型號： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁數(shù)： | 83/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應(yīng)用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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www.austriamicrosystems.com
Revision 1.11
83 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
5
HP_OVC
(level)
0
W
Headphone over-current interrupt setting
0: disable
1: enable
The interrupt must not be enabled if the headphone block is
disabled
x
R
Headphone over-current interrupt reading
0: no over-current detected
1: headphone over-current detected, headphone amplifier was
shut down. The current thresholds are 150mA at HPR / HPL
pin or 300mA at HPCM pin.
4
I2S_status
x
R
0: no LRCK on I2S interface detected
1: LRCK on I2S interface present
3
I2S_IRQ
0
W
I2S input status change interrupt setting
0: disable
1: enable
I2S_changed
(status change)
x
R
I2S input status change interrupt reading
0: I2S input status not changed
1: I2S input status changed, check I2S_status
2
VOXM_IRQ
0
W
Enables interrupt which is invoked by reaching a voltage
threshold at the MIC input (voice activation)
0: disable
1: enable
x
R
This bit is set when a voltage threshold of 5mVRMS (unfiltered)
at the MIC has been reached (voice activation)
1
MIC_CON
(level)
0
W
Microphone connect detection interrupt setting
0: disable
1: enable
x
R
Microphone connect detection interrupt reading
0: no microphone connected to MIC input
1: microphone connected at MIC input.
This interrupt is only invoked when the microphone stage is
powered down. The IRQ will be released after enabling the
microphone stage.
Detecting a microphone during operation has to be done by
measuring the supply current
0
HPH_CON
(level)
0
W
Headphone connect detection interrupt setting
0: disable
1: enable
x
R
Headphone connect detection interrupt reading
0: no headphone connected
1: headphone connected
This interrupt is only invoked when the headphone stage is
powered down. The IRQ will be released after enabling the
headphone stage.
Detecting a headphone during operation is not possible.
Table 85. Fourth Interrupt Register
Name
Base
Default
IRQENRD_3
2-wire serial
00h
Offset: 26h
Fourth Interrupt Register
Please be aware that writing to this register will enable/disable the
corresponding interrupts, while reading gets the actual interrupt status and
will clear the register at the same time. It is not possible to read back the
interrupt enable/disable settings. This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
ams
AG
Technical
content
still
valid
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