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Revision 1.11
79 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 82. First Interrupt Register
Name
Base
Default
IRQENRD_0
2-wire serial
00h
Offset: 23h
First Interrupt Register
Please be aware that writing to this register will enable/disable the
corresponding interrupts, while reading gets the actual interrupt status and
will clear the register at the same time. It is not possible to read back the
interrupt enable/disable settings. This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7
CVDD1_SD
0
W
Invokes shut-down of AFE when a –10% under-voltage spike
at CVDD1 occurs
0: disable
1: enable
CVDD1_under
x
R
This bit is set when a –5% under-voltage at CVDD1 occurs
6
CVDD1_IRQ
0
W
Enables interrupt for over-voltage/under-voltage supervision of
CVDD1
0: disable
1: enable
CVDD1_over
x
R
This bit is set when a +8% over-voltage at CVDD1 occurs
5:4
-
00
n/a
3
PVDD2_SD
0
W
Invokes shut-down of AFE when a –10% under-voltage spike
at PVDD2 occurs
0: disable
1: enable
PVDD2_under
x
R
This bit is set when a –5% under-voltage at PVDD2 occurs
2
PVDD2_IRQ
0
W
Enables interrupt for over-voltage/under-voltage supervision of
PVDD2
0: disable
1: enable
PVDD2_over
x
R
This bit is set when a +5% over-voltage at PVDD2 occurs
1
PVDD1_SD
0
W
Invokes shut-down of AFE when a –10% under-voltage spike
at PVDD1 occurs
0: disable
1: enable
PVDD1_under
x
R
This bit is set when a –5% under-voltage at PVDD1 occurs
0
PVDD1_IRQ
0
W
Enables interrupt for over-voltage/under-voltage supervision of
PVDD1
0: disable
1: enable
PVDD1_over
x
R
This bit is set when a +5% over-voltage at PVDD1 occurs
ams
AG
Technical
content
still
valid