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| 型號： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁數(shù)： | 71/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標準包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應商設備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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www.austriamicrosystems.com
Revision 1.11
72 - 91
AS3543 3v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 70. Out_Cntr3 Register
Name
Base
Default
Out_Cntr3
2-wire serial
00h
Offset: 1Ah-3
SDO and XIRQ Output Control Register
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7:6
DRIVE_SDO<1:0>
00
R/W
Sets the SDO output pin to push-pull or tri-state and sets
various driving strengths
00: 6mA push-pull output
01: HiZ, stri-state
10: 2mA push-pull output
11: 1mA push-pull output
5:4
MUX_SDO<1:0>
00
R/W
Multiplexes various digital signals to theSDO output pin
00: SDO, serial data output of the audio ADC
01: CLK24M, 24MHz oszillator output
10: CLKINT1, internal clock signal, see Clk_Cntr regsiter
11: PWM, PMW_Cntr register
3:2
DRIVE_XIRQ<1:0>
00
R/W
Sets the XIRQ output pin to open-drain, push-pull or tri-state
and sets various driving strengths
00: 6mA open-drain output
01: 6mA push-pull output
10: 1mA push-pull output
11: HiZ, stri-state
1:0
MUX_XIRQ<1:0>
00
R/W
Multiplexes various digital signals to the XRES output pin
00: XIRQ, active low interrupt request signal
01: CLKINT1, internal clock signal, see Clk_Cntr regsiter
10: CLKINT2, internal clock signal, see Clk_Cntr regsiter
11: IRQ, active low reset signal
Table 71. In_Cntr Register
Name
Base
Default
In_Cntr
2-wire serial
00h
Offset: 1Ah-4
HBT and Dimming Input Control Register
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a AVDD27-POR.
Bit
Bit Name
Default
Access
Bit Description
7:4
-
0000
n/a
3:2
MUX_HBT<1:0>
00
R/W
Selects the HBT (heartbeat) input pin
00: OFF, heartbeat input deactivated
01: PWGD pin
10: Q24M pin
11: Q32k pin
1:0
MUX_ExtDim<1:0>
00
R/W
Selects the input pin for external dimming of the DCDC15
00: OFF, no pin selected
In this mode the current sinks can be used without enabling
the DCDC15. ExtDim_ON bit has to be set in DCDC15
register.
01: PWGD pin
10: Q24M pin
11: Q32k pin
ams
AG
Technical
content
still
valid
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