參數資料
| 型號： | AS3543-ECTP |
| 廠商： | ams |
| 文件頁數： | 44/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AUDIO FRONT END 68CTBGA |
| 標準包裝： | 4,000 |
| 類型： | 音頻編解碼器 |
| 應用： | 便攜式音頻，電話 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-TFBGA |
| 供應商設備封裝： | 68-CTBGA（6x6） |
| 包裝： | 帶卷 (TR) |
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www.austriamicrosystems.com
Revision 1.11
48 - 91
AS3543 3v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
10.5
Real Time Clock
10.5.1 General
The real time clock block is an independent block, which is still working even when the chip is shut down. The only
condition for this operation is that BVDDR has a voltage of above 1.0V. The block uses a standard 32kHz crystal that is
connected to a low power oscillator. The total power consumption is typ. 650nA. (Q32K clock buffer not operating)
An internal supply switch will supply the RTC as long as possible form the Li-Ion battery and only switch to BVDDR if
the main battery is empty or has been removed.
The RTC seconds counter is 32bit wide and can be programmed via the 2-wire serial interface. The RTC can deliver a
second or minute interrupt.
Another 23bit wide counter allows auto wake-up (max. after 96 days). This counter is internally connected to the
power-up and hibernation control block.
The RTC voltage regulator (RVDD) further supplies a 128bit SRAM. It can be used to store settings or data before
shutdown.
The Q32K output can be configured to operate in push/pull (3 different driver strengths) or to be trie-state. For a more
detailed description of the GPIO functionality of this pin please refer to chapter GPIO Pins on page 50.
10.5.2 Clock Adjustment
The RTC clock is adjustable in steps of 7.6ppm which allows the use of inexpensive 32kHz crystals. The nominal fre-
quency shall be 32.768Hz. This frequency is divided down to 0.25Hz:
f = 32.768 / (4*32*1024)
At the input of this divider one can add corrective counts, which allow to correct an inaccurate crystal in a range from –
64 counts (=-488ppm) to +63 counts (=+480ppm):
fcorrected = fcrystal / [(4*32*1024)-64+RTC_TBC]
10.5.3 Register Description
Table 36. RTC Related Register
Name
Base
Offset
Description
2-wire serial
19h
RTC wake-up settings and SDRAM access
2-wire serial
1A-2h
Control of Q32K signal and drive
2-wire serial
1Ch
Enables writings to extended register 1Ah-2
2-wire serial
25h
Interrupt settings for RVDD under-voltage detection
2-wire serial
27h
Interrupt settings for getting a second or minute interrupt
2-wire serial
28h
RTC oscillator and counter enable, free usable bits
2-wire serial
29h
RTC interrupt and time correction settings
2-wire serial
2Ah to
2Dh
RTC time-base seconds registers
ams
AG
Technical
content
still
valid
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