- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366891 > CR16HCT5VJE7Y Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | CR16HCT5VJE7Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 121/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5VJE7Y |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)當(dāng)前第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
121
www.national.com
This register is initialized to 11 when a new
conversion is started (when ADCCNT2.START
is changed from 0 to 1) and is automatically in-
cremented every time a result is written to buff-
ers ADDATA0-ADDATA3. The result is a four-
entry cyclic FIFO buffer, with BUFPTR pointing
to the last entry written by the A/D Converter.
22.2.2
The ADCCNT1 register is a byte-wide, read/write register
used to enable the A/D Converter and its interrupts, and also
to control the reference voltage source. When writing to this
register, all reserved bits must be written with 0 for the A/D
Converter to function properly. Changing any bits other than
ADCEN (bit 0) is not allowed while the A/D Converter is ac-
tive (ADCST.BUSY or ADCCNT2.START set). Upon reset,
all non-reserved bits are cleared to 0. The register format is
shown below.
7
6
5
4
3
2
Reserved
INTE
ADC Control 1 Register (ADCCNT1)
ADCEN
A/D Converter Enable. Setting this bit enables
the A/D Converter and allows a conversion to
be
started
by
setting
(ADCCNT2.START). Clearing the ADCEN bit
disables the A/D Converter, terminates any
conversion in progress, and clears the ADC
status flags (ADCST.EOC, ADCST.BUSY,
ADCST.OVF, and ADCCNT2.START).
Interrupt Enable. This bit enables (1) or dis-
ables (0) A/D Converter interrupts. If enabled,
and interrupt occurs at the end of a conversion
sequence or when the ADC data buffer is full,
depending on the operating mode.
All reserved bits must be written with 0 for ADC to operate
properly.
the
start
bit
INTE
22.2.3
The ADCCNT2 register is a byte-wide, read/write register
used to specify the A/D Converter operating mode and to
start conversion operations. All register fields other than the
START bit should be changed only while the A/D Converter
is inactive (START=0). Data written to the SCAN and CONT
fields is ignored if the START bit is already set. Upon reset,
the non-reserved bits of this register are cleared to 0. The
register format is shown below.
7
6
5
START
SCAN
ADC Control 2 Register (ADCCNT2)
CHANNEL
Channel Select. This 4-bit field selects one of
the twelve analog input channels as follows:
0000 = ACH0
0001 = ACH1
0010 = ACH2
0011 = ACH3
0100 = ACH4
0101 = ACH5
0110 = ACH6
0111 = ACH7
1000 = ACH8
1001 = ACH9
1010 = ACH10
1011 = ACH11
11XX = reserved
Continuous Conversion. When cleared to 0,
the A/D Converter stops operating upon com-
pletion of the programmed conversion cycle (a
single conversion or a sequence of four con-
versions on four channels). When set to 1, the
A/D Converter operates continuously by re-
peating the programmed conversion cycle.
Scan Mode. This 2-bit field selects the single-
conversion mode or 4-channel scan mode as
follows:
00 = single-conversion mode
01 = 4-channel scan mode
1X = reserved
Start Conversion. The software sets this bit to 1
to start a conversion or a 4-channel conversion
cycle. In the “continuous” mode, this bit re-
mains set until cleared by the software. In the
“single” (non-continuous) mode, the hardware
clears this bit upon completion of the pro-
grammed conversion cycle. The software
should not attempt to set this bit while the A/D
Converter is busy (ADCST.BUSY=1).
CONT
SCAN
START
22.2.4
The ADCCNT3 register is a byte-wide, read/write register
used to specify the analog sampling time delay and the di-
vide-by factor for generating the ADC clock. This register
should be written only when the A/D Converter is disabled
(ADCCNT1.ADCEN=0). Upon reset, the non-reserved bits of
the ADCCNT3 register are cleared to 0. The register format
is shown below.
7
6
5
Reserved
PWREN
DELAY
ADC Control 3 Register (ADCCNT3)
CDIV
Clock Divide. This 3-bit field sets the divide-by
factor for generating the A/D Converter clock
from the system clock. The frequency of the A/
D Converter clock is equal to the system clock
divided by the programmed factor. The result-
ing A/D Converter clock frequency must be
less than or equal to 2 MHz. The divide-by fac-
tor is defined as follows:
000 = divide by 1
001 = divide by 2
010 = divide by 4
011 = divide by 8
100 = divide by 16
101 = divide by 32
Other = reserved
Sampling Time Delay. This 3-bit field defines
the number of A/D Converter clock cycles of
delay from the time that the input channel is se-
lected until the analog voltage is sampled. The
programmed delay should be sufficient, depen-
dent on the source impedance, to allow the
sampled signal to reach its final level before the
conversion begins. The delay is defined as fol-
lows:
DELAY
1
0
Reserved
ADCEN
4
3
2
1
0
CONT
CHANNEL
4
3
2
1
0
CDIV
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16HCT5VJE8Y | Microcontroller |
| CR16HCT5VJE9Y | Microcontroller |
| CR16HCT9 | |
| CR16HCT9VJE7 | Microcontroller |
| CR16HCT9VJE7Y | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16HCT5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT5VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。