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| 型號： | CR16HCT5VJE7Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 98/157頁 |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5VJE7Y |
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98
If the status is changed during BUSY being active, the status
is updated by the CR16CAN as shown in Table 21.
The buffer states are indicated and controlled by the ST[3:0]
bits in the CNSTAT register (see Buffer Status/Control Regis-
ter (CNSTAT) on page 105. The various receive buffer states
are explained in RX Buffer States on page 99.
20.5.2
The user has to execute the following procedure to initialize
a message buffer for the reception of a CAN message.
1. Configure the receive masks (GMASK or BMASK, re-
spectively).
2. Configure the buffer ID.
3. Configure the message buffer status as RX_READY.
In order to read the out of a received message, the CPU has
to execute the following steps (see Figure 62):
Receive Procedure
The first step is only applicable if polling is used to get the sta-
tus of the receive buffer. It can be deleted for an interrupt driv-
en receive routine.
1. Read the status (CNSTAT) of the receive buffer. If the
status is RX_READY, no was the message received, ex-
it. If the status is RX_BUSY, copy process from hidden
receive buffer is not completed yet, read CNSTAT again.
If a buffer is configured to RX_READY and its interrupt
is enabled, it will generate an interrupt as soon as the
buffer has received a message and entered the
RX_FULL state (see also Interrupts on page 102). In that
case the procedure described below should be followed.
2. Read the status to determine if a new message has
overwritten the one originally received which triggered
the interrupt.
3. Write RX_READY into CNSTAT.
4. Read the ID/data and object control (DLC/RTR) from the
message buffer.
5. Read the buffer status again and check it is not
RX_BUSYx. If it is, repeat this step until RX_BUSYx has
gone away.
6. If the buffer status is RX_FULL or RX_OVERRUN, one
or more messages were copied. In that case, start over
with step 2.
7. If status is still RX_READY (as set by the CPU at step 2),
clear interrupt pending bit and exit.
When the BUFFLOCK function is enabled (see BUFFLOCK
on page 96), it is not necessary to check for new messages
received during the read process from the buffer, as this buff-
er is locked after the reception of the first valid frame. A read
from a locked receive buffer can be performed as shown in
Figure 63.
For simplicity only the applicable interrupt routine is shown:
1. Read the ID/data and object control (DLC/RTR) from the
message buffer.
2. Write RX_READY into CNSTAT.
3. Clear interrupt pending bit and exit.
read buffer
read CNSTAT
RX_READY
RX_OVERRUN
RX_FULL or
RX_OVERRUN
Y
N
read buffer (id/data/cntrl)
write RX_READY
exit
Y
N
Y
N
Figure 62.
Buffer Read Routine (BUFFLOCK Disabled)
read CNSTAT
Interrupt Entry Point
clear RX_PND
A new message has
been received while
reading data from the
receive buffer
(optional, for information)
RX_BUSYx
RX_BUSYx
N
Y
read buffer (id/data/cntrl)
write RX_READY
exit
Figure 63.
Buffer Read Routine (BUFFLOCK Enabled)
Interrupt Entry Point
clear RX_PND
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| CR16HCT5VJE8Y | Microcontroller |
| CR16HCT5VJE9Y | Microcontroller |
| CR16HCT9 | |
| CR16HCT9VJE7 | Microcontroller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CR16HCT5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT5VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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