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| 型號(hào)： | CR16HCT5VJE7Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 31/157頁 |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5VJE7Y |
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10.0
Interrupts
The Interrupt Control Unit (ICU31L) receives interrupt re-
quests from internal and external sources and generates in-
terrupts to the CPU. Interrupts from the timers, USARTs,
MICROWIRE/SPI interface, Multi-Input Wake-Up, and A/D
converter are all maskable interrupts. The highest-priority in-
terrupt is the Non-Maskable Interrupt (NMI), which is trig-
gered by a falling edge received on the NMI input pin. The
NMI pin is not available on the 44-pin packages.
10.1
An
exception
is an event that temporarily stops the normal
flow of program execution and causes execution of a sepa-
rate service routine. Upon completion of the service routine,
execution of the interrupted program continues from the point
at which it was stopped.
There are two kinds of exceptions, called
traps
and
inter-
rupts
. A trap is the result of some action or condition in the
program itself, such as execution of an Exception (EXCP) in-
struction. An interrupt is a CPU-external event, such as a sig-
nal received on a Multi-Input Wake-Up input or a request
from an on-chip peripheral module for service.
The operation of traps is beyond the scope of this data sheet.
For information on traps, and for additional detailed informa-
tion on interrupts not provided in this data sheet, please refer
to the CompactRISC CR16B Programmer's Reference Man-
ual.
INTERRUPT OPERATION
10.1.1
When an interrupt occurs, the on-chip hardware performs the
following steps:
1. Decrements the Interrupt Stack Point (ISP) by four.
2. Saves the contents of the Program Counter (PC) and
Processor Status Register (PSR) on the interrupt stack.
3. Clears the I, P, and T bits in the Processor Status Regis-
ter (PSR). These are the Global Maskable Interrupt En-
able bit, Trace Trap Pending bit, and Trace bit,
respectively.
4. Reads the interrupt vector from the Interrupt Vector Reg-
ister (IVCT).
5. Combines the interrupt vector with the value in the Inter-
rupt Base (INTBASE) register to obtain an address in
the Interrupt Dispatch Table, and loads the dispatch ta-
ble entry into the Program Counter (PC).
From this point onward, the CPU executes the interrupt ser-
vice routine. The service routine ends with a Return from Ex-
ception (RETX) instruction. This returns the CPU to the
interrupted program. The CPU restores the contents of the
PC and PSR registers from the stack and increments the In-
terrupt Stack Pointer by four.
Interrupt Operation Summary
10.1.2
When an interrupt or trap occurs, the CPU executes a ser-
vice routine. There are different service routines for different
interrupts and traps. Each service routine may reside any-
where in program memory. The starting addresses of the ser-
vice routines are contained in a table called the Dispatch
Table. Entries in the table are organized in the order shown
in Table 10.
Service Routine Addresses
Table 10
Dispatch Table Entries
0: Reserved
1: NMI
2: Reserved
3: Reserved
4: Reserved
5: SVC (Supervisor Call Trap)
6: DVC (Divided by Zero Trap)
7: FLG (Flag Trap)
8: BPT (Breakpoint Trap)
9: TRC (Trace Trap)
10: UND (Undefined Instruction Trap)
11: Reserved
12: Reserved
13: Reserved
14: Reserved
15: Reserved
16: INT0 (Reserved)
17: INT1 (Flash EEPROM Program Memory)
18: INT2 (Reserved)
19: INT3 (Reserved)
20: INT4 (Reserved)
21: INT5 (ADC)
22: INT6 (MIWU Interrupt 3)
23: INT7 (MIWU Interrupt 2)
24: INT8 (MIWU Interrupt 1)
25: INT9 (MIWU Interrupt 0)
26: INT10 (USART 2 Tx)
27: INT11 (USART 1Tx)
28: INT12 (Reserved)
29: INT13 (MICROWIRE/SPI Rx/TX)
30: INT14 (ACCESS.bus)
31: INT15 (USART 2 Rx)
32: INT16 (USART 1 Rx)
33: INT17 (Reserved)
34: INT18 (CAN)
35: INT19 (Reserved)
36: INT20 (Reserved)
37: INT21 (Reserved)
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相關(guān)代理商/技術(shù)參數(shù) |
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| CR16HCT5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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| CR16HCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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