參數(shù)資料
型號： CR16HCT5VJE7Y
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 21/157頁
文件大?。?/td> 1256K
代理商： CR16HCT5VJE7Y
21
www.national.com
8.3.5
Table 8 is a summary showing the number of access cycles
used for various address ranges.
Access Timing Summary Table
8.3.6
Table 9 shows the recommended register settings for various
clock rates. Different clock rates require different register set-
tings because the flash EEPROM program memories have
Recommended Register Settings
specific setup and hold requirements that can be met only by
using enough wait cycles and hold cycles.
Between clock rates of 10 MHz and 20MHz, the number of
wait states required for memory access (either none or one)
depends on the desired power mode of the program memory.
Table 8
Access Timing Table
Address
Range (hex)
Memory or
I/O Type
Access Cycles
read
write
0000-BFFF
Flash EEPROM Program
Memory
SZCFG0.FRE=1:
1 cycle
SZCFG0.FRE=1:
1 cycle
+ BCFG.EWR
(+ programming time)
SZCFG0.FRE=0:
2 cycles
+ BCFG.EWR
+ SZCFG0.WAIT
+ SZCFG0.HOLD
(+ programming time)
1 cycle
MCFG.ZEROWS=1:
1 cycle
(+ programming time)
MCFG.ZEROWS=0:
2 cycles
(+ programming time)
2 cycles
SZCFG0.FRE=0:
2 cycles
+ SZCFG0.WAIT
+ SZCFG0.HOLD
C000-CBFF
F000-F27F
Static RAM Memory
EEPROM Data Memory
1 cycle
MCFG.ZEROWS=1:
1 cycle
MCFG.ZEROWS=0:
2 cycles
F900-FFFF
F800-F9FF
FC00-FFFF
FB00-FBFF
On-Chip Peripherals
2 cycles
Ports B and C
3 cycle
+ IOCFG.WAIT
+ IOCFG.HOLD
3 cycle
+ BCFG.EW
+ IOCFG.WAIT
+ IOCFG.HOLD
Table 9
Recommended Register Settings
Clock Rate
SZCFG0
SZCFG1
IOCFG
< 10 MHz,
0 wait state
10 to 20MHz,
0 wait state
10 to 20MHz,
1 wait state
> 20 MHz,
1 wait state
0880 hex
0880 hex
0080 hex
0880 hex
0880 hex
0080 hex
0080 hex
0080 hex
0080 hex
0080 hex
0080 hex
0080 hex
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CR16HCT5VJE8Y 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
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