參數(shù)資料
型號： CR16HCT5VJE7Y
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 63/157頁
文件大?。?/td> 1256K
代理商： CR16HCT5VJE7Y
63
www.national.com
flag will be updated regardless of the value of
the IxAEN bit.
0
Enable system interrupt request for the
IxAPD pending flag
1
Disable system interrupt request for the
IxAPD pending flag
Timer x interrupt B enable. Enable/Disable an
interrupt request based on the corresponding
IxBPD flag being set. The associated IxBPD
flag will be updated regardless of the value of
the IxBEN bit.
0
Enable system interrupt request for the
IxBPD pending flag
1
Disable system interrupt request for the
IxBPD pending flag
Timer x interrupt C enable. Enable/Disable an
interrupt request based on the corresponding
IxCPD flag being set. The associated IxCPD
flag will be updated regardless of the value of
the IxCEN bit.
0
Enable system interrupt request for the
IxCPD pending flag
1
Disable system interrupt request for the
IxCPD pending flag
Timer x interrupt D enable. Enable/Disable an
interrupt request based on the corresponding
IxDPD flag being set. The associated IxDPD
flag will be updated regardless of the value of
the IxDEN bit.
0
Enable system interrupt request for the
IxDPD pending flag
1
Disable system interrupt request for the
IxDPD pending flag
IxBEN
IxCEN
IxDEN
16.2.5
The Interrupt Pending (INTPND) register is a word-wide
read/write register which contains all 16 interrupt pending
flags. There are four interrupt pending flags called IxAPD
through IxDPD per timer subsystem. Each interrupt pending
flag is set by a hardware event and can be cleared if the user
software writes a 1 to the bit position. The value will remain
unchanged if a 0 is written to the bit position. All interrupt
pending flags are cleared (0) upon reset.
15
14
13
12
I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD
Interrupt Pending Register (INTPND)
IxAPD
Timer x interrupt A pending. If set (1), indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 17 on page 61
lists the hardware condition which causes this
bit to be set.
Timer x interrupt B pending. If set (1), indicates
that an interrupt condition for the related timer
IxBPD
subsystem has occurred. Table 17 on page 61
lists the hardware condition which causes this
bit to be set.
Timer x interrupt C pending. If set (1), indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 17 on page 61
lists the hardware condition which causes this
bit to be set.
Timer x interrupt D pending. If set (1), indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 17 on page 61
lists the hardware condition which causes this
bit to be set.
IxCPD
IxDPD
16.2.6
CLK1PS is a word-wide read/write register. The register is
split into two 8-bit wide field called C1PRSC and C2PRSC.
Each field holds the 8-bit clock prescaler compare value for
timer subsystems 1 and 2 respectively. The register is
cleared upon reset.
15
8 7
C2PRSC
Clock Prescaler Register 1 (CLK1PS)
C1PRSC
Clock Prescaler 1 compare value. Holds the 8-
bit prescaler value for timer subsystem 1. The
counter of timer subsystem is incremented
each time when the clock prescaler compare
value matches the value of the clock prescaler
counter. The divide-by-ratio is equal to
C1PRSC+1 i.e. a value of 00
16
results in a di-
vide by 1 whereas the maximum divide-by ratio
is 256 for a C1PRSC value of FF
16
.
Clock Prescaler 2 compare value. Holds the 8-
bit prescaler value for timer subsystem 2. The
functionality of this field is identical to the one
described for C1PRSC in the previous para-
graph.
C2PRSC
16.2.7
The Clock Prescaler Register 2 (CLK2PS) is a word-wide
read/write register. The register is split into two 8-bit wide
fields called C3PRSC and C4PRSC. Each field holds the 8-
bit clock prescaler compare value for timer subsystems 3 and
4 respectively. The register is cleared upon reset.
15
8 7
C4PRSC
Clock Prescaler Register 2 (CLK2PS)
C3PRSC
Clock Prescaler 3 compare value. Holds the 8-
bit prescaler value for timer subsystem 3. The
functionality of this field is identical to the one
described for C1PRSC on page 63.
Clock Prescaler 4 compare value. Holds the 8-
bit prescaler value for timer subsystem 4. The
functionality of this field is identical to the one
described for C1PRSC on page 63.
C4PRSC
16.2.8
The Counter (COUNTx) registers are word wide read/write
registers. There are a total of four registers called COUNT1
through COUNT4, one for each of the four timer subsystems.
The user software may read the registers at any time. Read-
Counter Registers (COUNTx)
11
10
9
8
7
6
5
4
3
2
1
0
I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD
0
C1PRSC
0
C3PRSC
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參數(shù)描述
CR16HCT5VJE8Y 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
CR16HCT5VJE9Y 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
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CR16HCT9VJE7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
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