參數(shù)資料
型號: CY7C1248KV18-400BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 2M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 10/28頁
文件大?。?/td> 907K
代理商: CY7C1248KV18-400BZXC
CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Document Number: 001-57834 Rev. *B
Page 18 of 28
Identification Register Definitions
Instruction Field
Value
Description
CY7C1246KV18
CY7C1257KV18
CY7C1248KV18
CY7C1250KV18
Revision number
(31:29)
000
Version number.
Cypress device ID
(28:12)
11010111100000111 11010111100001111 11010111100010111 11010111100100111 Defines the type of
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
Allows unique
identification of
SRAM vendor.
ID register
presence (0)
1
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
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