參數(shù)資料
型號(hào)： CY7C1248KV18-400BZXC
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 2M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 2/28頁(yè)
文件大?。?/td> 907K
代理商： CY7C1248KV18-400BZXC
CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Document Number: 001-57834 Rev. *B
Page 10 of 28
Valid Data Indicator (QVLD)
QVLD is provided on the DDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power-up, when the DOFF is tied HIGH, the PLL is locked after
20
s of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20
s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR I mode (with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
Application Example
Figure 1 shows two DDR II+ used in an application.
Figure 1. Application Example
DQ
A
SRAM#2
LD
CQ/CQ
K
ZQ
K
R/W BWS
BUS
MASTER
(CPU or ASIC)
DQ
Addresses
LD
R/W
R = 250ohms
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
R = 250ohms
BWS
DQ
A
SRAM#1
LD
K
ZQ
CQ/CQ
K
R/W BWS
相關(guān)PDF資料
PDF描述
CY7C1371AV25-66AC 512K X 36 ZBT SRAM, 10 ns, PQFP100
CY7C1387DV25-225BZI 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
CY7C1387DV25-225BZC 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
CY7C138AV Memory
CY7C025-15JC x16 Dual-Port SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1248KV18-450BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (2Mx18) 1.8v 450MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C12501KV 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C12501KV18-400BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb x 36 400 MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C12501KV18-400BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mb x 36 400 MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C12501KV18-450BZXC 功能描述:IC SRAM 36MBIT 450MHZ 165-FPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類(lèi)型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線(xiàn)串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*