參數(shù)資料
型號: CY7C1248KV18-400BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 2M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 16/28頁
文件大?。?/td> 907K
代理商: CY7C1248KV18-400BZXC
CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Document Number: 001-57834 Rev. *B
Page 23 of 28
AC Electrical Characteristics
Over the Operating Range [25]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH voltage
VREF + 0.2
VDDQ + 0.24
V
VIL
Input LOW voltage
–0.24
VREF – 0.2
V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
Max
Unit
CIN
Input capacitance
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
4
pF
CO
Output capacitance
4pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
165 FBGA
Package
Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and procedures for
measuring thermal impedance, in accordance with EIA/JESD51.
13.7
°C/W
JC
Thermal resistance
(junction to case)
3.73
°C/W
Figure 4. AC Test Loads and Waveforms
1.25 V
0.25 V
R = 50
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device
RL = 50
Z0 = 50
VREF = 0.75 V
0.75 V
Under
Test
0.75 V
Device
Under
Test
OUTPUT
0.75 V
VREF
OUTPUT
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
(b)
RQ =
250
Notes
25. Overshoot: VIH(AC) < VDDQ + 0.3 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
26. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input pulse
levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
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