參數(shù)資料
型號: CY7C1248KV18-400BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 2M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 18/28頁
文件大?。?/td> 907K
代理商: CY7C1248KV18-400BZXC
CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Document Number: 001-57834 Rev. *B
Page 25 of 28
Switching Waveforms
Read/Write/Deselect Sequence [35, 36, 37, 38]
Figure 5. Waveform for 2.0 Cycle Read Latency
DON’T CARE
UNDEFINED
1
2
3
4
5
6
7
8
9
10
READ
NOP
WRITE
t
NOP
11
K
LD
R/W
A
tKH tKL
tCYC
tHC
tSA tHA
SC
A0
A1
A2
A3
A4
CQ
QVLD
t
NOP
t
QVLD
t
tCCQO
tCQOH
t
tCQOH
QVLD
t
NOP
DQ
KHKH
12
(Read Latency = 2.0 Cycles)
NOP
CCQO
tSD
HD
tSD
tHD
t
CLZ
tCHZ
D20 D21
D30
D31
t
CQDOH
Q00
Q11
Q01 Q10
tDOH
tCO
Q40 Q41
tCQD
t
tCQH
CQHCQH
Notes
35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
36. Outputs are disabled (high Z) one clock cycle after a NOP.
37. The third NOP cycle between read to write transition is not necessary for correct device operation when read latency = 2.0 cycles; however at high frequency operation,
it is required to avoid bus contention.
38. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
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