參數(shù)資料
型號： CY7C1248KV18-400BZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 2M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù)： 26/28頁
文件大?。?/td> 907K
代理商： CY7C1248KV18-400BZXC
CY7C1246KV18, CY7C1257KV18
CY7C1248KV18, CY7C1250KV18
Document Number: 001-57834 Rev. *B
Page 7 of 28
Table 2. Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input output-
synchronous
Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is deselected,
Q[x:0] are automatically tristated.
CY7C1246KV18
DQ[7:0]
CY7C1257KV18
DQ[8:0]
CY7C1248KV18
DQ[17:0]
CY7C1250KV18
DQ[35:0]
LD
Input-
synchronous
Synchronous load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
NWS0,
NWS1
Input-
synchronous
Nibble write select 0, 1
active LOW (CY7C1246KV18 only). Sampled on the rising edge of the K and
K clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
synchronous
Byte write select 0, 1, 2, and 3
active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1257KV18
BWS0 controls D[8:0]
CY7C1248KV18
BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1250KV18
BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
synchronous
Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4 M × 8 (2 arrays each of 2 M × 8) for CY7C1246KV18 and 4 M × 9 (2 arrays each of 2 M × 9) for
CY7C1257KV18, 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1248KV18, and 1 M × 36 (2 arrays each
of 512 K × 36) for CY7C1250KV18.
R/W
Input-
synchronous
Synchronous read or write input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD
Valid output
indicator
Valid output indicator. The Q valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
K
Input clock
Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input clock
Negative input clock input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0].
CQ
Echo clock
Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24.
CQ
Echo clock
Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
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CY7C12501KV18-400BZC 功能描述:靜態(tài)隨機存取存儲器 1Mb x 36 400 MHz Sync 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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