參數(shù)資料
型號： DK-DEV-4SGX230N
廠商： Altera
文件頁數(shù)： 11/82頁
文件大?。?/td> 0K
描述： KIT DEVELOPMENT STRATIX IV
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Stratix? IV GX FPGA Development Kit
標準包裝： 1
系列： Stratix® IV GX
類型： FPGA
適用于相關產(chǎn)品： EP4SGX230K
所含物品： 開發(fā)板、通用電源、纜線和軟件
產(chǎn)品目錄頁面： 607 (CN2011-ZH PDF)
相關產(chǎn)品： EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA
EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA
其它名稱： 544-2594
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–11
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Hot Socketing
Table 1–15 lists the hot socketing specifications for Stratix IV devices.
Internal Weak Pull-Up Resistor
Table 1–16 lists the weak pull-up resistor values for Stratix IV devices.
COUTFB
Input capacitance on the dual-purpose clock output and feedback pins
5
pF
CCLK1, CCLK3, CCLK8,
and CCLK10
Input capacitance for dedicated clock input pins
2
pF
Table 1–14. Pin Capacitance for Stratix IV Devices (Part 2 of 2)
Symbol
Description
Value
Unit
Table 1–15. Hot Socketing Specifications for Stratix IV Devices
Symbol
Description
Maximum
IIOPIN (DC)
DC current per I/O pin
300
A
IIOPIN (AC)
AC current per I/O pin
8 mA (1)
I
XCVR-TX (DC)
DC current per transceiver TX pin
100 mA
I
XCVR-RX (DC)
DC current per transceiver RX pin
50 mA
Note to Table 1–15:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Table 1–16. Internal Weak Pull-Up Resistor for Stratix IV Devices (1), (3)
Symbol
Description
Conditions (V)
Value (4)
Unit
RPU
Value of the I/O pin pull-up resistor before
and during configuration, as well as user
mode if the programmable pull-up resistor
option is enabled.
VCCIO = 3.0 ±5% (2)
25
k
VCCIO = 2.5 ±5% (2)
25
k
VCCIO = 1.8 ±5% (2)
25
k
VCCIO = 1.5 ±5% (2)
25
k
VCCIO = 1.2 ±5% (2)
25
k
Notes to Table 1–16:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(3) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is
approximately 25 k
(4) These specifications are valid with ±10% tolerances to cover changes over PVT.
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