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| 型號： | DK-DEV-4SGX230N |
| 廠商： | Altera |
| 文件頁數(shù)： | 66/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEVELOPMENT STRATIX IV |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 特色產(chǎn)品： | Stratix? IV GX FPGA Development Kit |
| 標準包裝： | 1 |
| 系列： | Stratix® IV GX |
| 類型： | FPGA |
| 適用于相關產(chǎn)品： | EP4SGX230K |
| 所含物品： | 開發(fā)板、通用電源、纜線和軟件 |
| 產(chǎn)品目錄頁面： | 607 (CN2011-ZH PDF) |
| 相關產(chǎn)品： | EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA |
| 其它名稱： | 544-2594 |
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–61
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Table 1–49 lists the memory output clock jitter specifications for Stratix IV devices.
OCT Calibration Block Specifications
Table 1–50 lists the OCT calibration block specifications for Stratix IV devices.
Table 1–49. Memory Output Clock Jitter Specification for Stratix IV Devices (1), (2), (3), (4)
Parameter
Clock
Network
Symbol
–2/–2X
Speed Grade
–3
Speed Grade
–4
Speed Grade
Unit
Min
Max
Min
Max
Min
Max
Clock period jitter
Regional
t
JIT(per)
-5050-55
55-5555
ps
Cycle-to-cycle period jitter
Regional
t
JIT(cc)
-100
100
-110
110
-110
110
ps
Duty cycle jitter
Regional
t
JIT(duty)
-50
50
-82.5
82.5
-82.5
82.5
ps
Clock period jitter
Global
t
JIT(per)
-75
75
-82.5
82.5
-82.5
82.5
ps
Cycle-to-cycle period jitter
Global
t
JIT(cc)
-150
150
-165
165
-165
165
ps
Duty cycle jitter
Global
t
JIT(duty)
-7575-90
90-9090
ps
Notes to Table 1–49:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL
output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
(3) The memory output clock jitter stated in Table 1–49 is applicable when an input jitter of 30 ps is applied.
(4) The clock jitter specification is characterized with 70% utilization, 266 MHz core clock frequency, and 12.5% design toggle rate. If your design
exceeds any of these conditions, the jitter specification of the design may not meet the above specification.
Table 1–50. OCT Calibration Block Specifications for Stratix IV Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
20
MHz
TOCTCAL
Number of OCTUSRCLK clock cycles required for OCT RS/RT
calibration
—
1000
—
Cycles
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
—
28
—
Cycles
TRS_RT
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between OCT RS and RT
—2.5
—
ns
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DK-DEV-4SGX230N/C2 | 功能描述:EP4SGX230KF40C2N Stratix? IV GX FPGA Evaluation Board 制造商:altera 系列:Stratix? IV GX 零件狀態(tài):過期 類型:FPGA 配套使用產(chǎn)品/相關產(chǎn)品:EP4SGX230KF40C2N 內(nèi)容:板，線纜，電源 標準包裝:1 |
| DK-DEV-4SGX530N | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For EP4SGX530 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-5AGTD7N | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For 5AGTD7K3F40I3N RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-5AGXB3N/ES | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For 5AGXFB3H6F ES RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-5ASTD5N | 功能描述:KIT DEV ARRIA V FPGA 制造商:altera 系列:Arria V ST 零件狀態(tài):在售 類型:FPGA 配套使用產(chǎn)品/相關產(chǎn)品:Arria? V ST 內(nèi)容:板 標準包裝:1 |
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