參數(shù)資料
型號(hào)： DK-DEV-4SGX230N
廠(chǎng)商： Altera
文件頁(yè)數(shù)： 50/82頁(yè)
文件大?。?/td> 0K
描述： KIT DEVELOPMENT STRATIX IV
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Stratix? IV GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： Stratix® IV GX
類(lèi)型： FPGA
適用于相關(guān)產(chǎn)品： EP4SGX230K
所含物品： 開(kāi)發(fā)板、通用電源、纜線(xiàn)和軟件
產(chǎn)品目錄頁(yè)面： 607 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA
EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA
其它名稱(chēng)： 544-2594
1–46
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
Table 1–32 lists the SFI-S transmitter jitter specifications for Stratix IV GT devices.
Sinusoidal Jitter
tolerance
Jitter Frequency = 40 KHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
> 5
—
UI
Jitter Frequency
4MHz
Pattern = PRBS-31
Equalization = Disabled
BER = 1E-12
> 0.05
—
UI
Notes to Table 1–31:
(1) The jitter numbers for XLAUI/CAUI are compliant to the IEEE P802.3ba specification.
(2) Stratix IV GT transceivers are compliant to the XFI datacom transmitter jitter specifications in Table 9 of XFP Revision 4.1.
(3) Contact Altera for board and link best practices at BER = 1E-15.
Table 1–31. Transceiver Jitter Specifications for Protocols by Stratix IV GT Devices (Part 2 of 2)
Symbol/
Description
Conditions
–1 Industrial Speed
Grade
–2 Industrial Speed
Grade
–3 Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Table 1–32. SFI-S Transmitter Jitter Specifications for Stratix IV GT Devices (1), (2)
Symbol/Description
Conditions
-1 Industrial
Speed Grade
-2 Industrial
Speed Grade
-3 Industrial
Speed Grade
Unit
Mean
Total Transmitter jitter at
11.3 Gbps (4)
Pattern = PRBS-31
Vod = 800 mV
REFCLK = 706.25 MHz
12 channels in Basic ×1 mode
0.23 UI (3)
——
UI
Notes to Table 1–32:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers are valid for stated conditions only.
(3) Two hundred channels were characterized to derive the mean transmitter jitter specification of 0.23 UI. The maximum jitter across the 200 units
characterized was 0.30 UI.
(4) Contact Altera for board and link best practices at BER = 1E-15.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DK-DEV-4SGX230N/C2 功能描述:EP4SGX230KF40C2N Stratix? IV GX FPGA Evaluation Board 制造商:altera 系列:Stratix? IV GX 零件狀態(tài):過(guò)期 類(lèi)型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:EP4SGX230KF40C2N 內(nèi)容:板，線(xiàn)纜，電源 標(biāo)準(zhǔn)包裝:1
DK-DEV-4SGX530N 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For EP4SGX530 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓:
DK-DEV-5AGTD7N 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For 5AGTD7K3F40I3N RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓:
DK-DEV-5AGXB3N/ES 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For 5AGXFB3H6F ES RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓:
DK-DEV-5ASTD5N 功能描述:KIT DEV ARRIA V FPGA 制造商:altera 系列:Arria V ST 零件狀態(tài):在售 類(lèi)型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:Arria? V ST 內(nèi)容:板 標(biāo)準(zhǔn)包裝:1
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