參數(shù)資料
型號： DK-DEV-4SGX230N
廠商： Altera
文件頁數(shù)： 48/82頁
文件大小： 0K
描述： KIT DEVELOPMENT STRATIX IV
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Stratix? IV GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： Stratix® IV GX
類型： FPGA
適用于相關(guān)產(chǎn)品： EP4SGX230K
所含物品： 開發(fā)板、通用電源、纜線和軟件
產(chǎn)品目錄頁面： 607 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA
EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA
其它名稱： 544-2594
1–44
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
Sinusoidal Jitter
tolerance at 3072 Mbps
Jitter Frequency = 21.8
KHz
Pattern = CJPAT
> 8.5
UI
Jitter Frequency =
1843.2 MHz to 20 MHz
Pattern = CJPAT
> 0.1
UI
Notes to Table 1–30:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The Jitter numbers are valid for the stated conditions only.
(3) Stratix IV GX devices in military speed grade only support selected transceiver configuration up to 3125 Mbps. For more information, contact
Altera sales representative.
(4) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(5) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(6) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(7) The jitter numbers for PCI Express (PIPE) (PCIe) are compliant to the PCIe Base Specification 2.0.
(8) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(9) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(10) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(11) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(13) The fibre channel transmitter jitter generation numbers are compliant to the specification at
T interoperability point.
(14) The fibre channel receiver jitter tolerance numbers are compliant to the specification at
R interoperability point.
(15) You must use the ATX PLL adjacent to the transceiver channels to meet the transmitter jitter generation compliance in PCIe Gen2 ×8 modes.
(16) Stratix IV PCIe receivers are compliant to this specification provided the VTX-CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50mV.
(17) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(18) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(19) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices (1), (2) (Part 9 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial
and –2× Commercial
Speed Grade
–3 Military (3) and
–4 Commercial/
Industrial Speed
Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
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參數(shù)描述
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