參數(shù)資料
型號: DK-DEV-4SGX230N
廠商: Altera
文件頁數(shù): 71/82頁
文件大?。?/td> 0K
描述: KIT DEVELOPMENT STRATIX IV
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品: Stratix? IV GX FPGA Development Kit
標準包裝: 1
系列: Stratix® IV GX
類型: FPGA
適用于相關產(chǎn)品: EP4SGX230K
所含物品: 開發(fā)板、通用電源、纜線和軟件
產(chǎn)品目錄頁面: 607 (CN2011-ZH PDF)
相關產(chǎn)品: EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA
EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA
其它名稱: 544-2594
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–65
Glossary
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
J
J
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing
Specifications
JTAG Timing Specifications:
K, L,
M, N, O
——
P
PLL
Specifications
Diagram of PLL Specifications (1)
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Q
——
RRL
Receiver differential input discrete resistor (external to Stratix IV device).
Table 1–54. Glossary Table (Part 2 of 4)
Letter
Subject
Definitions
TDO
TCK
tJPZX
t
JPCO
tJPH
t JPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS
Core Clock
External Feedback
Reconfigurable in User Mode
Key
CLK
N
M
PFD
Switchover
VCO
CP
LF
CLKOUT Pins
GCLK
RCLK
fINPFD
fIN
fVCO
fOUT
fOUT_EXT
Counters
C0..C9
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