參數(shù)資料
型號: DS3112+
廠商: Maxim Integrated Products
文件頁數(shù): 70/133頁
文件大?。?/td> 0K
描述: IC MUX TEMPE T3/E3 256-BGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: 調幀器,多路復用器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 150mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應商設備封裝: 256-PBGA(27x27)
包裝: 管件
產(chǎn)品目錄頁面: 1419 (CN2011-ZH PDF)
DS3112
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device detects a clock at FTCLK. The HRCLK checks for the presence of the FTCLK. On reset, both the LOTC
and LORC status bits will be set and then immediately cleared if the clock is present.
Bit 11: Loss Of Receive Clock Detected (LORC). This read-only real-time status bit will be set to a one when the
device detects that the HRCLK clock has not toggled for 200ns (±100ns). This bit will be cleared when a clock is
detected at the HRCLK input. The setting of this status bit can cause a hardware interrupt to occur if the LORC bit
in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the
device detects a clock at HRCLK. The FTCLK checks for the presence of the HRCLK. On reset, both the LOTC
and LORC status bits will be set and then immediately cleared if the clock is present.
Bit 12: State of the T3E3MS Input Signal (T3E3MS). This read-only real-time status bit reflects the current state
of the external T3E3MS input signal. This status bit cannot generate an interrupt.
Bit 13: State of the G.747E Input Signal (G.747E). This read-only real-time status bit reflects the current state of
the external G.747E input signal. This status bit cannot generate an interrupt.
Figure 4-4. BERT Status Bit Flow
Alarm Latch
Change in State Detect
RLOS
(BERTEC0
Bit 4)
Internal RLOS
Signal from
BERT
Event Latch
Internal Bit
Error Detected
Signal from
BERT
Event Latch
Internal Counter
Overflow
Signal from
BERT
OR
BED
(BERTEC0
Bit 3)
BECO or BBCO
(BERTEC0
Bits 1 & 2)
Mask
BERT
(IMSR Bit 2)
INT*
Hardware
Signal
BERT
Status Bit
(MSR Bit 2)
Mask
IESYNC (BERTC0 Bit 15)
Mask
IEBED (BERTC0 Bit 14)
IEOF (BERTC0 Bit 13)
Event Latch
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE BERTEC0 REGISTER IS READ.
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