參數(shù)資料
型號： DS3112+
廠商： Maxim Integrated Products
文件頁數(shù)： 83/133頁
文件大?。?/td> 0K
描述： IC MUX TEMPE T3/E3 256-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
控制器類型： 調(diào)幀器，多路復(fù)用器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 150mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-PBGA（27x27）
包裝： 管件
產(chǎn)品目錄頁面： 1419 (CN2011-ZH PDF)
DS3112
53 of 133
5.5 T3/E3 Framer Status and Interrupt Register Description
Register Name:
T3E3SR
Register Description:
T3/E3 Status Register
Register Address:
12h
Bit #
7
6
5
4
3
2
1
0
Name
—
RSOF
TSOF
T3IDLE
RAI
AIS
LOF
LOS
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
—
Default
—
Note: See Figure 5-1 for details on the signal flow for the status bits in the T3E3SR register. Bits that are underlined are read-only. All
others are read-write.
Bit 0: Loss Of Signal Occurrence (LOS). This latched read-only alarm-status bit will be set to a one when the T3
or E3 framer detects a loss of signal. This bit will be cleared when read unless a LOS condition still exists. A
change in state of the LOS can cause a hardware interrupt to occur if the LOS bit in the Interrupt Mask for T3E3SR
(IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when this bit is read. The LOS alarm criteria are described in Table 5-1
and Table 5-2.
Bit 1: Loss Of Frame Occurrence (LOF). This latched read-only alarm status bit will be set to a one when the T3
or E3 framer detects a loss of frame. This bit will be cleared when read unless a LOF condition still exists. A
change in state of the LOF can cause a hardware interrupt to occur if the LOF bit in the Interrupt Mask for T3E3SR
(IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when this bit is read. The LOF alarm criteria are described in Table 5-1
Bit 2: Alarm Indication Signal Detected (AIS). This latched read-only alarm-status bit will be set to a one when
the T3 or E3 framer detects an incoming Alarm Indication Signal. This bit will be cleared when read unless an AIS
signal is still present. A change in state of the AIS detection can cause a hardware interrupt to occur if the AIS bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read. The AIS alarm
detection criteria is described in Table 5-1 and Table 5-2.
Bit 3: Remote Alarm Indication Detected (RAI). This latched read-only alarm status bit will be set to a one when
the T3 or E3 framer detects an incoming Remote Alarm Indication (RAI) signal. This bit will be cleared when read
unless an RAI signal is still present. A change in state of the RAI detection can cause a hardware interrupt to occur
if the RAI bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
The RAI alarm detection criteria are described in Table 5-1 and Table 5-2. RAI can also be indicated via the FEAC
codes when the device is operated in the C-Bit Parity Mode.
Bit 4: T3 Idle Signal Detected (T3IDLE). This latched read-only alarm status bit will be set to a one when the T3
framer detects an incoming idle signal. This bit will be cleared when read unless the idle signal is still present. A
change in state of idle detection can cause a hardware interrupt to occur if the IDLE bit in the Interrupt Mask for
T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is
set to a one. The IDLE detection criteria are described in Table 5-1. The interrupt will be allowed to clear when this
bit is read. When the DS3112 is operated in the E3 mode, this status bit should be ignored.
Bit 5: Transmit T3/E3 Start Of Frame (TSOF). This latched read-only event-status bit will be set to a one on
each T3/E3 transmit frame boundary. This bit is a software version of the FTSOF hardware signal and it will be
cleared when read. The setting of this bit can cause a hardware interrupt to occur if the TSOF bit in the Interrupt
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參數(shù)描述
DS3112+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
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