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參數(shù)資料
| 型號(hào)： | DS3134 |
| 英文描述： | Chateau Channelized T1 And E1 And HDLC Controller |
| 中文描述： | 不推薦用于新設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 10/203頁(yè) |
| 文件大?。?/td> | 777K |
| 代理商： | DS3134 |
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DS3134
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DATA SHEET DEFINITIONS
Table 1B
Acronym
Or Term
Definition
BERT
Descriptor
Dword
DMA
FIFO
HDLC
Host
n/a
V.54
Bit Error Rate Tester.
A message passed back and forth between the DMA and the Host.
Double Word. A 32-bit data entity.
Direct Memory Access.
First In First Out. Temporary memory storage scheme.
High level Data Link Control.
The main controller that resides on the PCI Bus.
Not Assigned.
A pseudorandom pattern used to control loopbacks (see ANSI T1.403)
GOVERNING SPECIFICATIONS
Table 1C
ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1
Metallic Interface March 21, 1995.
PCI Local Bus Specification V2.1 June 1, 1995.
GENERAL DESCRIPTION
The Layer One Block handles the physical input and output of serial data to and from the DS3134. The
DS3134 is capable of handling up to 64 T1 or E1 data streams or 2 T3 data streams. Each of the 16
physical ports can handle up to two or four T1 or E1 data streams. Section 14 contains some examples of
how this is performed. The Layer One Block prepares the incoming data for the HDLC Block and grooms
data from the HDLC Block for transmission. The block has the ability to perform both channelized and
unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer One Block that the
Host will enable HDLC channels and assign them to a particular port and/or DS0 channel(s). The Host
assigns HDLC channels via the R[n]CFG[j] and T[n]CFG[j] registers, which are described in Section 5.3.
The Layer One Block interfaces directly to the Bit Error Rate Tester (BERT) Block. The BERT Block
can generate and detect both pseudorandom and repeating bit patterns and it is used to test and stress data
communication links.
The HDLC Block consists of two types of HDLC controllers. There are 16 Slow HDLC Engines (one for
each port) that are capable of operating at speeds up to 8.192 Mbps in channelized mode and up to
10 Mbps in unchannelized mode. There are also two Fast HDLC Engines, which only reside on Ports 0
and 1 and they are capable of operating at speeds up to 52 Mbps. Via the RP[n]CR and TP[n]CR
registers in the Layer One Block, the Host will configure Port 0 and 1 to use either the Slow or the Fast
HDLC engine. The HDLC Engines perform all of the Layer 2 processing which include, zero stuffing
and destuffing, flag generation and detection, CRC generation and checking, abort generation and
checking.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3171N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3172N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
| DS31400DK | 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 DS31400 Dev Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| DS31400GN | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Not Available From Mouser RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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