參數(shù)資料
型號(hào)： DS3134
英文描述： Chateau Channelized T1 And E1 And HDLC Controller
中文描述： 不推薦用于新設(shè)計(jì)
文件頁(yè)數(shù)： 130/203頁(yè)
文件大?。?/td> 777K
代理商： DS3134
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DS3134
130 of 203
Transmit Packet Descriptors
Figure 8.2.2B
dword 0
Data Buffer Address (32)
dword 1
EOF
dword 2
CV
unused
Byte Count (13)
Next Descriptor Pointer (16)
unused (24)
HDLC Channel (8)
dword 3
unused (15)
PV
Next Pending Descriptor Pointer (16)
Note:
1.
The organization of the Transmit Descriptor is not affected by the enabling of Big Endian
2.
The format of the Transmit Descriptor is almost identical to the Receive Descriptor; this lessens the
burden of the Host in preparing descriptors in store-and-forward applications
3.
Next Descriptor pointer is an index and not an absolute address.
dword 0; Bits 0 to 31 / Data Buffer Address.
Direct 32-bit starting address of the data buffer that is associated
with this transmits descriptor.
dword 1; Bits 0 to 15 / Next Descriptor Pointer.
This 16-bit value is the offset from the Transmit Descriptor
Base Address of the next descriptor in the chain. Only valid if EOF = 0 (next descriptor in the same packet chain)
or if EOF = 1 and CV = 1 (first descriptor in the next packet).
dword 1; Bits 16 to 28 / Byte Count.
Number of bytes stored in the data buffer. Maximum is 8191 bytes (0000h
= 0 bytes / 1FFFh = 8191 bytes).
dword 1; Bit 29 / Unused.
This bit is ignored by the transmit DMA and can be set to any value.
dword 1; Bit 30 / Chain Valid (CV).
If CV is set to a one when EOF = 1, then this indicates that the Next
Descriptor Pointer field is valid and corresponds to the first descriptor of the next packet that is queued up for
transmission. The CV bit is ignored when EOF = 0.
dword 1; Bit 31 / End Of Frame (EOF).
When set to a one, this bit indicates that the descriptor is the last
buffer in the current packet. When set to a zero, this bit indicates that Next Descriptor Pointer field is valid and
points to the next descriptor in the packet chain.
dword 2; Bits 0 to 7 / HDLC Channel Number.
HDLC channel number, which can be from 1 to 256.
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256
dword 2; Bits 8 to 31 / Unused.
These bits are ignored by the transmit DMA and can be set to any value.
dword 3; Bits 0 to 15 / Next Pending Descriptor Pointer.
This 16-bit value is the offset from the Transmit
Descriptor Base Address to another the descriptor chain that is queued up for transmission. The transmit DMA
can store up to 2 queued packet chains internally but additional packet chains must be stored as a link list by the
transmit DMA using this field. This field is only valid if PV = 1 and it should be set to 0000h by the Host when
the Host is preparing the descriptor.
dword 3; Bit 16 / Pending Descriptor Valid (PV).
If set, this bit indicates that the Next Pending Descriptor
Pointer field is valid and corresponds to the first descriptor of the next packet chain that is queued up for
transmission. This field is written to by the transmit DMA to link descriptors together and should always be set to
0 by the Host.
dword 3; Bits 17 to 31 / Unused.
These bits are ignored by the transmit DMA and can be set to any value.
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