參數(shù)資料
型號： DS32512DK
廠商： Maxim Integrated Products
文件頁數(shù)： 105/130頁
文件大小： 0K
描述： KIT DEMO FOR DS32512
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計資源： DS32512 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS32512
DS32506/DS32508/DS32512
76 of 130
Register Name:
LIU.SRL
Register Description:
LIU Status Register Latched
Register Address:
n * 80h + 2Ah
Bit #
15
14
13
12
11
10
9
8
Name
—
JAFL
JAEL
TDML
TFAILL
LOMCL
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
—
RGLCL
RPASL
RFAIL1L
RFAIL2L
RLOLL
ALOSL
Default
0
Bit 12: Jitter Attenuator Full Latched (JAFL).
This bit is set when the jitter attenuator buffer is full, or when data
has been lost due to a jitter attenuator buffer underflow or overflow. When set, this bit causes an interrupt if
interrupt enables LIU.SRIE:JAFIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.4.
Bit 11: Jitter Attenuator Empty Latched (JAEL).
This bit is set when the jitter attenuator buffer is empty, or when
data has been lost due to a jitter attenuator buffer underflow or overflow. When set, this bit causes an interrupt if
interrupt enables LIU.SRIE:JAEIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.4.
Bit 10: Transmit Driver Monitor Change Latched (TDML).
This bit is set when the LIU.SR:TDM bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:TDMIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 9: Transmit Output Failure Change Latched (TFAILL).
This bit is set when the LIU.SR:TFAIL bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:TFAILIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 8: Loss of Master Clock Latched (LOMCL).
This bit is set when the LIU.SR:LOMC bit is set. When set, this
bit causes an interrupt if interrupt enables LIU.SRIE:LOMCIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE
are all set.
Bit 5: Receive Gain Level Change Latched (RGLCL).
This bit is set when the receive gain level (LIU.RGLR:
RGL[7:0]) changes. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RGLCIE,
Bit 4: Receive Preamp Status Change Latched (RPASL).
This bit is set when the LIU.SR:RPAS bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RPASIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 3: Receive Failure Type 1 Change Latched (RFAIL1L).
This bit is set when the LIU.SR:RFAIL1 bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RFAIL1IE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 2: Receive Failure Type 2 Change Latched (RFAIL2L).
This bit is set when the LIU.SR:RFAIL2 bit changes
state. When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RFAIL2IE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 1: Receive Loss of Lock Change Latched (RLOLL).
This bit is set when the LIU.SR:RLOL bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:RLOLIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 0: Analog Loss of Signal Change Latched (ALOSL).
This bit is set when the LIU.SR:ALOS bit changes state.
When set, this bit causes an interrupt if interrupt enables LIU.SRIE:ALOSIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
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