參數(shù)資料
型號: DS32512DK
廠商: Maxim Integrated Products
文件頁數(shù): 121/130頁
文件大小: 0K
描述: KIT DEMO FOR DS32512
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計資源: DS32512 Gerber Files
標準包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS32512
DS32506/DS32508/DS32512
90 of 130
Register Name:
BERT.RBECR2
Register Description:
BERT Receive Bit Error Count Register #2
Register Address:
n * 80h + 66h
Bit #
15
14
13
12
11
10
9
8
Name
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
BEC[23:16]
Default
0
Bits 7 to 0: Bit Error Count (BEC[23:16])
Bit Error Count (BEC[23:0]).
This field is the holding register for an internal BERT bit error counter that tracks the
number of bit errors detected in the incoming data stream since the last performance monitoring update. The
internal counter stops incrementing when it reaches a count of FF FFFFh and does not increment when an OOS
condition exists. This register is updated when a performance monitoring update is performed. See Section 8.7.4.
The source for the performance monitoring update signal is specified by the BERT.CR:PMUM bit.
Register Name:
BERT.RBCR1
Register Description:
BERT Receive Bit Count Register #1
Register Address:
n * 80h + 68h
Bit #
15
14
13
12
11
10
9
8
Name
BC[15:8]
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
BC[7:0]
Default
0
Bits 15 to 0: Bit Count (BC[15:0])
Register Name:
BERT.RBCR2
Register Description:
BERT Receive Bit Count Register #2
Register Address:
n * 80h + 6Ah
Bit #
15
14
13
12
11
10
9
8
Name
BC[31:24]
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
BC[23:16]
Default
0
Bits 15 to 0: Bit Count (BC[31:16])
Bit Count (BC[31:0]).
This field is the holding register for an internal BERT bit counter that tracks the total number
of bit received in the incoming data stream since the last performance monitoring update. The internal counter
stops incrementing when it reaches a count of FFFF FFFFh and does not increment when an OOS condition
exists. This register is updated when a performance monitoring update is performed. See Section 8.7.4. The
source for the performance monitoring update signal is specified by the BERT.CR:PMUM bit.
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