參數(shù)資料
型號(hào): DS32512DK
廠商: Maxim Integrated Products
文件頁數(shù): 79/130頁
文件大小: 0K
描述: KIT DEMO FOR DS32512
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計(jì)資源: DS32512 Gerber Files
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS32512
DS32506/DS32508/DS32512
52 of 130
Register Name:
GLOBAL.CR1
Register Description:
Global Control Register #1
Register Address:
002h
Bit #
15
14
13
12
11
10
9
8
Name
G1SRS[3:0]
G1SROE
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
TMEI
MEIMS
GPM[1:0]
GPMU
RSTDP
RST
Default
0
1
0
Bits 12 to 9: Global One-Second Reference Source (G1SRS[3:0]).
These bits determine the source for the
internally generated one second reference. The source is selected from one of the CLAD clocks or from one of the
port transmit clocks. See Section 8.7.2.
0000 = Disabled
0001 = DS3 reference clock
0010 = E3 reference clock
0011 = STS-1 reference clock
0100 = Port 1 TCLK
0101 = Port 2 TCLK
0110 = Port 3 TCLK
0111 = Port 4 TCLK
1000 = Port 5 TCLK
1001 = Port 6 TCLK
1010 = Port 7 TCLK
1011 = Port 8 TCLK
1100 = Port 9 TCLK
1101 = Port 10 TCLK
1110 = Port 11 TCLK
1111 = Port 12 TCLK
Bit 8: Global One-Second Reference Output Enable (G1SROE).
This bit determines whether the GPIOB3 pin is
used to output the global one second reference signal. See Section 8.7.2.
0 = GPIOB3 pin mode selected by GLOBAL.GIOBCR1:GIOB3S[1:0].
1 = GPIOB3 outputs the global one second reference signal specified by GLOBAL.CR1:G1SRS[3:0]
Bit 7: Transmit Manual Error Insert (TMEI).
When GLOBAL.CR1:MEIMS = 0, this bit is used to insert errors in all
blocks in all ports where block-level MEIMS = 1 and PORT.CR1:MEIMS = 1. Error(s) are inserted at the next
opportunity after this bit transitions from low to high. See Section 8.7.5. Note: This bit should be set low
immediately after each error insertion.
Bit 6: Manual Error Insert Mode Select (MEIMS).
This bit specifies the source of the manual error insertion signal
for all block-level error generators that have block-level MEIMS = 1 and PORT.CR1:MEIMS = 1. See Section 8.7.5.
0 = Global error insertion using GLOBAL.CR1:TMEI bit
1 = Global error insertion using the GPIOB2 pin
Bits 5 and 4: Global Performance Monitor Update Mode (GPM[1:0]).
These bits specify the source of the
performance monitoring update signal for all blocks that have block-level PMUM = 1 and PORT.CR1:PMUM = 1.
See Section 8.7.4.
00 = Global PM update using the GLOBAL.CR1:GPMU bit
01 = Global PM update using the GPIOB1 pin
1X = One-second PM update using the internal one-second counter (see Section 8.7.2)
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