參數(shù)資料
型號： DS32512DK
廠商： Maxim Integrated Products
文件頁數(shù)： 111/130頁
文件大?。?/td> 0K
描述： KIT DEMO FOR DS32512
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計資源： DS32512 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS32512
DS32506/DS32508/DS32512
81 of 130
Register Name:
LINE.RSR
Register Description:
B3ZS/HDB3 Receive Status Register
Register Address:
n * 80h + 44h
Bit #
15
14
13
12
11
10
9
8
Name
—
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
—
EXZC
—
BPVC
LOS
Default
0
Bit 3: Excessive Zero Count (EXZC).
See Section 8.3.6.
0 = the Receive Excessive Zero Count Register (LINE.REXZCR) is zero
1 = the Receive Excessive Zero Count Register (LINE.REXZCR) is one or more
Bit 1: Bipolar Violation Count (BPVC).
See Section 8.3.6.
0 = the Receive Bipolar Violation Count Register (LINE.RBPVCR) is zero
1 = the Receive Bipolar Violation Count Register (LINE.RBPVCR) is one or more
Bit 0: Loss of Signal (LOS).
See Section 8.3.5.
0 = receive line interface is not in a LOS condition
1 = receive line interface is in an LOS condition
Register Name:
LINE.RSRL
Register Description:
B3ZS/HDB3 Receive Status Register Latched
Register Address:
n * 80h + 46h
Bit #
15
14
13
12
11
10
9
8
Name
—
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
—
ZSCDL
EXZL
EXZCL
BPVL
BPVCL
LOSL
Default
0
Bit 5: Zero Suppression Code Detect Latched (ZSCDL).
This bit is set when a B3ZS or HDB3 signature is
detected. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:ZSCDIE, PORT.ISRIE:LDSRIE
and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 4: Excessive Zero Latched (EXZL).
This bit is set when an excessive zero event is detected on the incoming
bipolar data stream. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:EXZIE,
PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 3: Excessive Zero Count Latched (EXZCL).
This bit is set when LINE.RSR:EXZC transitions from zero to
one. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:EXZCIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 2: Bipolar Violation Latched (BPVL).
This bit is set when a bipolar violation (or E3 LCV if enabled) is detected
on the incoming bipolar data stream. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:BPVIE,
PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 1: Bipolar Violation Count Latched (BPVCL).
This bit is set when LINE.RSR:BPVC transitions from zero to
one. When set, this bit causes an interrupt if interrupt enables LINE.RSRIE:BPVCIE, PORT.ISRIE:LDSRIE and
GLOBAL.ISRIE:PnISRIE are all set. See Section 8.3.6.
Bit 0: Loss of Signal Change Latched (LOSL).
This bit is set when LINE.RSR:LOS changes state. When set, this
bit causes an interrupt if interrupt enables LINE.RSRIE:LOSIE, PORT.ISRIE:LDSRIE and GLOBAL.ISRIE:PnISRIE
are all set. See Section 8.3.5.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS32512N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512N# 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512NA2 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube
DS32512NW 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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