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參數(shù)資料
| 型號： | DS32512DK |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 60/130頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEMO FOR DS32512 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 設(shè)計資源： | DS32512 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，線路接口單元（LIU） |
| 已用 IC / 零件： | DS32512 |
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DS32506/DS32508/DS32512
35 of 130
Figure 8-6. DS3 and E3 Wander Tolerance
10
100
0.13
DS325xx
Wander Tolerance
Wan
der
Tole
ra
nc
e(UI
p-
p)
Frequency (Hz)
1
1000
4.4
34.4
10-1
10-2
137.5
0.032
G.823 (E3)
G.824 (DS3)
67
1.675
805
10-3
10-4
10-5
1.2
6.12
8.3.10 Jitter Transfer
Without the jitter attenuator on the receive side, the receiver attenuates jitter at frequencies above its corner
frequency (approximately 300kHz) and passes jitter at lower frequencies. With the jitter attenuator enabled on the
receive side, the receiver meets the jitter transfer requirements of all applicable telecommunication standards in
Table 1-1. See Figure 8-7.
8.4 Jitter Attenuator
Each LIU contains an on-board jitter attenuator that can be placed in the receive path or the transmit path or can
be disabled. When only the hardware interface is enabled (IFSEL = 000 and HW = 1), the JAS[1:0] and JAD[1:0]
pins specify the specify the JA location and buffer depth for all ports. When a microprocessor interface is enabled
≠ 000), the JAS[1:0] and JAD[1:0] pins are ignored, and the LIU.CR1:JAS[1:0] and JAD[1:0] configuration
bits specify the JA location and buffer depth for each port individually. The JA buffer depth can be set to 16, 32, 64
or 128 bits. Figure 8-7 shows the minimum jitter attenuation for the device when the jitter attenuator is enabled.
Figure 8-7 also shows the receive jitter transfer when the jitter attenuator is disabled.
The jitter attenuator consists of a narrowband PLL to retime the selected clock, a FIFO to buffer the associated
data while the clock is being retimed, and logic to prevent FIFO over/underflow in the presence of very large jitter
amplitudes. The JA has a loop bandwidth of reference_clock
÷ 2,058,874 (see corner frequencies in Figure 8-7).
The JA attenuates jitter at frequencies higher than the loop bandwidth, while allowing jitter (and wander) at lower
frequencies to pass through relatively unaffected.
The jitter attenuator requires a transmission-quality reference clock (i.e.,
±20ppm frequency accuracy and low
jitter). See Section 8.7.1 for more information about reference clocks and clock selection.
When the microprocessor interface is enabled, the jitter attenuator indicates the fill status of its FIFO buffer in the
LIU.SRL:JAFL (JA full) and LIU.SRL:JAEL (JA empty) status bits. When the buffer becomes full, the JA
momentarily increases the frequency of the read clock by 6250ppm to avoid buffer overflow and consequent data
errors. When the buffer becomes empty, the JA momentarily decreases the frequency of the read clock by
6250ppm to avoid buffer underflow and consequent data errors. During these momentary frequency adjustments,
jitter is passed through the JA to avoid over/underflow. If the phase noise or frequency offset of the write clock is
large enough to cause the buffer to overflow or underflow, the JA sets both the JAFL bit and the JAEL bit to
indicate that data errors have occurred. JAFL and JAEL can cause an interrupt if enabled by the corresponding
enable bits in the LIU.SRIE register.
As shown in Figure 8-7, the jitter attenuator meets the jitter transfer requirements of all applicable standards listed
in Table 1-1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS32512N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS32512NA2 | 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube |
| DS32512NW | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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