參數(shù)資料
型號: DS32512DK
廠商: Maxim Integrated Products
文件頁數(shù): 117/130頁
文件大?。?/td> 0K
描述: KIT DEMO FOR DS32512
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計資源: DS32512 Gerber Files
標準包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS32512
DS32506/DS32508/DS32512
87 of 130
Register Name:
BERT.TEICR
Register Description:
BERT Transmit Error Insertion Control Register
Register Address:
n * 80h + 58h
Bit #
15
14
13
12
11
10
9
8
Name
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
TEIR[2:0]
BEI
TSEI
MEIMS
Default
0
Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]).
This field indicates the rate at which errors are
automatically inserted in the output data stream. One out of every 10
n bits is inverted, where n = TEIR[2:0]. A value
of 0 disables error insertion. A value of 1 results in every 10th bit being inverted. A value of 2 result in every 100th
bit being inverted. Error insertion starts when this field is written with a non-zero value. If this field is written during
an error insertion, the new error rate is used after the next error is inserted. See Section 8.5.3.1.
Bit 2: Bit Error Insertion Enable (BEI).
See Section 8.5.3.1.
0 = single-bit error insertion is disabled
1 = single-bit error insertion is enabled
Bit 1: Transmit Single Error Insert (TSEI).
When BERT.TEICR:MEIMS = 0 and BEI = 1, this bit is used to insert
single-bit errors in the outgoing BERT data stream. A zero-to-one transition causes a single bit error to be inserted.
For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and this bit
transitions more than once between error insertion opportunities, only one error is inserted. See Section 8.7.5.
Bit 0: Manual Error Insert Mode Select (MEIMS).
This bit specifies the source of the error insertion signal for the
BERT block. Note: If TMEI or TSEI is one, changing the state of this bit may cause a bit error to be inserted. See
Section 8.7.5.
0 = error insertion is initiated by the BERT.TEICR:TSEI register bit
1 = error insertion is initiated by the transmit manual error insertion signal (TMEI) specified by the
PORT.CR1:MEIMS register bit.
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