參數(shù)資料
型號： DS32512DK
廠商： Maxim Integrated Products
文件頁數(shù)： 47/130頁
文件大小： 0K
描述： KIT DEMO FOR DS32512
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計資源： DS32512 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS32512
DS32506/DS32508/DS32512
23 of 130
Table 7-9. JTAG Pin Descriptions
NAME
TYPE
FUNCTION
JTCLK
I
JTAG Clock. This pin shifts data into JTDI on the rising edge and out of JTDO on the
falling edge. JTCLK is typically a low frequency (less than 10MHz) 50% duty cycle clock
signal. If boundary scan is not used, JTCLK should be pulled high. See Section 10.
JTMS
Ipu
JTAG Mode Select. This pin is used to control the JTAG controller state machine. JTMS
is sampled on the rising edge of JTCLK. If boundary scan is not used, JTMS should be
left unconnected or pulled high. See Section 10.
JTDI
Ipu
JTAG Data Input. This pin is used to input data into the register that is enabled by the
JTAG controller state machine. JTDI is sampled on the rising edge of JTCLK. If boundary
scan is not used, JTDI should be left unconnected or pulled high. See Section 10.
JTDO
Oz
JTAG Data Output. This pin is the output of an internal scan shift register enabled by
the JTAG controller state machine. JTDO is updated on the falling edge of JTCLK. JTDO
is in high-impedance mode when a register is not selected or when the JTRST pin is low.
JTDO goes into and out of high-impedance mode after the falling edge of JTCLK. See
Section 10.
JTRST
Ipu
JTAG Reset (Active Low). When active, this pin forces the JTAG controller logic into
the reset state and forces the JTDO pin into high-impedance mode. The JTAG controller
is also reset when power is first applied via a power-on reset circuit. JTRST can be driven
high or low for normal operation, but must be high for JTAG operation. See Section 10.
Table 7-10. Power-Supply Pin Descriptions
NAME
TYPE
FUNCTION
VDD18
P
Digital Core 1.8V Power, 1.8V
±5%
VDD33
P
I/O 3.3V Power, 3.3V
±5%
VSS
P
Ground for VDD18 and VDD33
JVDDn
P
Jitter Attenuator 1.8V Power, 1.8V
±5%
JVSSn
P
Jitter Attenuator Ground
RVDDn
P
Receive 1.8V Power, 1.8V
±5%
RVSSn
P
Receive Ground
TVDDn
P
Transmit 1.8V Power, 1.8V
±5%
TVSSn
P
Transmit Ground
CVDD
P
CLAD 1.8V
±5%
CVSS
P
CLAD Ground
Table 7-11. Manufacturing Test Pin Descriptions
NAME
TYPE
FUNCTION
MT[10:0]
Test
Manufacturing Test Pins 10 to 0. MT[0] and MT[2:10] must not be connected. MT[1]
must be connected to digital ground (same as VSS pins).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS32512N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512N# 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512NA2 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube
DS32512NW 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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