±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, T
參數(shù)資料
型號： DS32512DK
廠商： Maxim Integrated Products
文件頁數(shù)： 129/130頁
文件大?。?/td> 0K
描述： KIT DEMO FOR DS32512
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設計資源： DS32512 Gerber Files
標準包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS32512
DS32506/DS32508/DS32512
98 of 130
Table 11-8. Parallel CPU Interface Timing
(VDD18 = 1.8V
±5%, VDD33 = 3.3V ±5%, AVDD = 1.8V ±5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL MIN TYP MAX
UNITS
Setup Time for A[10:0] Valid to RD, WR, or DS Active (Notes 1, 2)
t1
0
ns
Setup Time for CS Active to RD, WR, or DS Active
t2
0
ns
Delay Time from RD or DS Active to D[15:0] Valid Without RDY/ACK
Handshake
t3a
65
ns
Delay Time from RDY or ACK Active to D[15:0] Valid
t3b
20
ns
Hold Time from RD, WR, or DS Inactive to CS Inactive
t4
0
ns
Delay from CS, RD, or DS Inactive to D[15:0] Invalid (Note 3)
t5
2
ns
Wait Time from WR or DS Active to Latch D[15:0] Without RDY/ACK
Handshake
t6a
65
ns
Wait Time from RDY or ACK Active to Latch D[15:0]
t6b
20
ns
D[15:0] Setup Time to WR or DS Inactive
t7
10
ns
D[15:0] Hold Time from WR or DS Inactive
t8
2
ns
A[10:0] Hold Time from WR, RD, or DS Inactive
t9a
5
ns
Delay from WR, RD, or DS Inactive to ALE Active
t9b
20
ns
RD, WR, or DS Inactive Time
t10
75
ns
Muxed Address Valid to ALE Inactive (Note 4)
t11
10
ns
Muxed Address Hold Time from ALE Inactive (Note 4)
t12
10
ns
ALE Pulse Width (Note 4)
t13
20
ns
Setup Time for ALE High or Muxed Address Valid to CS Active
(Notes 4, 5, 6)
t14
0
ns
Delay from CS Inactive to D[15:0] Disable
t15
15
ns
Delay from CS Active to RDY/ACK Enable
t16
15
ns
Delay from CS, RD, WR, or DS Inactive to RDY/ACK Inactive (Note 7)
t17
2
ns
Delay from CS Inactive to RDY/ACK Disable
t18
15
ns
Note 1:
D[15:0] loaded with 50pF when tested as outputs.
Note 2:
If a gapped clock is applied on TCLK and local loopback is enabled, read cycle time must be extended by the length of the largest
TCLK gap.
Note 3:
Not tested during production test.
Note 4:
In nonmultiplexed bus applications (Figure 11-3 to Figure 11-6), ALE should be wired high. In multiplexed bus applications (Figure
11-7 to Figure 11-10), A[10:0] should be wired to D[15:0] and the falling edge of ALE latches the address.
Note 5:
t14 starts at the occurrence of the rising edge of ALE or A[10:0] valid whichever occurs later.
Note 6:
In order to avoid bus contention, during a read cycle A[10:0] should be disabled prior to RD or DS being active.
Note 7:
RDY/ACK may be disabled (t18) before going inactive (t17).
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DS32512N 功能描述:網(wǎng)絡控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512N# 功能描述:網(wǎng)絡控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512N+ 功能描述:網(wǎng)絡控制器與處理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS32512NA2 制造商:Maxim Integrated Products 功能描述:DS32512 X12 DS3/E3 LIU REVA2 IND - Rail/Tube
DS32512NW 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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