參數(shù)資料
型號: EPF10K100EQI208-2
廠商: Altera
文件頁數(shù): 25/100頁
文件大?。?/td> 0K
描述: IC FLEX 10K FPGA 100K 208-PQFP
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 72
系列: FLEX-10KE®
LAB/CLB數(shù): 624
邏輯元件/單元數(shù): 4992
RAM 位總計: 49152
輸入/輸出數(shù): 147
門數(shù): 257000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
30
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 14. FLEX 10KE Interconnect Resources
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. In some cases, using an LE register for an input register will
result in a faster setup time than using an IOE register. IOEs can be used
as input, output, or bidirectional pins. For bidirectional registered I/O
implementation, the output register should be in the IOE, and the data
input and output enable registers should be LE registers placed adjacent
to the bidirectional pin. The Altera Compiler uses the programmable
inversion option to invert signals from the row and column interconnect
automatically where appropriate. Figure 15 shows the bidirectional I/O
registers.
I/O Element (IOE)
Row
Interconnect
IOE
Column
Interconnect
LAB
B1
See Figure 17
for details.
See Figure 16
for details.
LAB
A3
LAB
B3
LAB
A1
LAB
A2
LAB
B2
IOE
Cascade &
LAB B4
LAB
A4
LAB B5
LAB
A5
IOE
Carry Chains
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